1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <asm/io.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/mach-imx/sys_proto.h>
13 #include <env.h>
14 #include <netdev.h>
15 #ifdef CONFIG_FSL_ESDHC_IMX
16 #include <fsl_esdhc_imx.h>
17 #endif
18
19 #ifdef CONFIG_FSL_ESDHC_IMX
20 DECLARE_GLOBAL_DATA_PTR;
21 #endif
22
23 static char soc_type[] = "xx0";
24
25 #ifdef CONFIG_MXC_OCOTP
enable_ocotp_clk(unsigned char enable)26 void enable_ocotp_clk(unsigned char enable)
27 {
28 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
29 u32 reg;
30
31 reg = readl(&ccm->ccgr6);
32 if (enable)
33 reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
34 else
35 reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
36 writel(reg, &ccm->ccgr6);
37 }
38 #endif
39
get_mcu_main_clk(void)40 static u32 get_mcu_main_clk(void)
41 {
42 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
43 u32 ccm_ccsr, ccm_cacrr, armclk_div;
44 u32 sysclk_sel, pll_pfd_sel = 0;
45 u32 freq = 0;
46
47 ccm_ccsr = readl(&ccm->ccsr);
48 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
49 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
50
51 ccm_cacrr = readl(&ccm->cacrr);
52 armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
53 armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
54 armclk_div += 1;
55
56 switch (sysclk_sel) {
57 case 0:
58 freq = FASE_CLK_FREQ;
59 break;
60 case 1:
61 freq = SLOW_CLK_FREQ;
62 break;
63 case 2:
64 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
65 pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
66 if (pll_pfd_sel == 0)
67 freq = PLL2_MAIN_FREQ;
68 else if (pll_pfd_sel == 1)
69 freq = PLL2_PFD1_FREQ;
70 else if (pll_pfd_sel == 2)
71 freq = PLL2_PFD2_FREQ;
72 else if (pll_pfd_sel == 3)
73 freq = PLL2_PFD3_FREQ;
74 else if (pll_pfd_sel == 4)
75 freq = PLL2_PFD4_FREQ;
76 break;
77 case 3:
78 freq = PLL2_MAIN_FREQ;
79 break;
80 case 4:
81 pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
82 pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
83 if (pll_pfd_sel == 0)
84 freq = PLL1_MAIN_FREQ;
85 else if (pll_pfd_sel == 1)
86 freq = PLL1_PFD1_FREQ;
87 else if (pll_pfd_sel == 2)
88 freq = PLL1_PFD2_FREQ;
89 else if (pll_pfd_sel == 3)
90 freq = PLL1_PFD3_FREQ;
91 else if (pll_pfd_sel == 4)
92 freq = PLL1_PFD4_FREQ;
93 break;
94 case 5:
95 freq = PLL3_MAIN_FREQ;
96 break;
97 default:
98 printf("unsupported system clock select\n");
99 }
100
101 return freq / armclk_div;
102 }
103
get_bus_clk(void)104 static u32 get_bus_clk(void)
105 {
106 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
107 u32 ccm_cacrr, busclk_div;
108
109 ccm_cacrr = readl(&ccm->cacrr);
110
111 busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
112 busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
113 busclk_div += 1;
114
115 return get_mcu_main_clk() / busclk_div;
116 }
117
get_ipg_clk(void)118 static u32 get_ipg_clk(void)
119 {
120 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
121 u32 ccm_cacrr, ipgclk_div;
122
123 ccm_cacrr = readl(&ccm->cacrr);
124
125 ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
126 ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
127 ipgclk_div += 1;
128
129 return get_bus_clk() / ipgclk_div;
130 }
131
get_uart_clk(void)132 static u32 get_uart_clk(void)
133 {
134 return get_ipg_clk();
135 }
136
get_sdhc_clk(void)137 static u32 get_sdhc_clk(void)
138 {
139 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
140 u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
141 u32 freq = 0;
142
143 ccm_cscmr1 = readl(&ccm->cscmr1);
144 sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
145 sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
146
147 ccm_cscdr2 = readl(&ccm->cscdr2);
148 sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
149 sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
150 sdhc_clk_div += 1;
151
152 switch (sdhc_clk_sel) {
153 case 0:
154 freq = PLL3_MAIN_FREQ;
155 break;
156 case 1:
157 freq = PLL3_PFD3_FREQ;
158 break;
159 case 2:
160 freq = PLL1_PFD3_FREQ;
161 break;
162 case 3:
163 freq = get_bus_clk();
164 break;
165 }
166
167 return freq / sdhc_clk_div;
168 }
169
get_fec_clk(void)170 u32 get_fec_clk(void)
171 {
172 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
173 u32 ccm_cscmr2, rmii_clk_sel;
174 u32 freq = 0;
175
176 ccm_cscmr2 = readl(&ccm->cscmr2);
177 rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
178 rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
179
180 switch (rmii_clk_sel) {
181 case 0:
182 freq = ENET_EXTERNAL_CLK;
183 break;
184 case 1:
185 freq = AUDIO_EXTERNAL_CLK;
186 break;
187 case 2:
188 freq = PLL5_MAIN_FREQ;
189 break;
190 case 3:
191 freq = PLL5_MAIN_FREQ / 2;
192 break;
193 }
194
195 return freq;
196 }
197
get_i2c_clk(void)198 static u32 get_i2c_clk(void)
199 {
200 return get_ipg_clk();
201 }
202
get_dspi_clk(void)203 static u32 get_dspi_clk(void)
204 {
205 return get_ipg_clk();
206 }
207
get_lpuart_clk(void)208 u32 get_lpuart_clk(void)
209 {
210 return get_uart_clk();
211 }
212
mxc_get_clock(enum mxc_clock clk)213 unsigned int mxc_get_clock(enum mxc_clock clk)
214 {
215 switch (clk) {
216 case MXC_ARM_CLK:
217 return get_mcu_main_clk();
218 case MXC_BUS_CLK:
219 return get_bus_clk();
220 case MXC_IPG_CLK:
221 return get_ipg_clk();
222 case MXC_UART_CLK:
223 return get_uart_clk();
224 case MXC_ESDHC_CLK:
225 return get_sdhc_clk();
226 case MXC_FEC_CLK:
227 return get_fec_clk();
228 case MXC_I2C_CLK:
229 return get_i2c_clk();
230 case MXC_DSPI_CLK:
231 return get_dspi_clk();
232 default:
233 break;
234 }
235 return -1;
236 }
237
238 /* Dump some core clocks */
do_vf610_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])239 int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
240 char * const argv[])
241 {
242 printf("\n");
243 printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
244 printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
245 printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
246
247 return 0;
248 }
249
250 U_BOOT_CMD(
251 clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
252 "display clocks",
253 ""
254 );
255
256 #ifdef CONFIG_FEC_MXC
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)257 __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
258 {
259 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
260 struct fuse_bank *bank = &ocotp->bank[4];
261 struct fuse_bank4_regs *fuse =
262 (struct fuse_bank4_regs *)bank->fuse_regs;
263
264 u32 value = readl(&fuse->mac_addr0);
265 mac[0] = (value >> 8);
266 mac[1] = value;
267
268 value = readl(&fuse->mac_addr1);
269 mac[2] = value >> 24;
270 mac[3] = value >> 16;
271 mac[4] = value >> 8;
272 mac[5] = value;
273 }
274 #endif
275
get_cpu_rev(void)276 u32 get_cpu_rev(void)
277 {
278 return MXC_CPU_VF610 << 12;
279 }
280
281 #if defined(CONFIG_DISPLAY_CPUINFO)
get_reset_cause(void)282 static char *get_reset_cause(void)
283 {
284 u32 cause;
285 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
286
287 cause = readl(&src_regs->srsr);
288 writel(cause, &src_regs->srsr);
289
290 if (cause & SRC_SRSR_POR_RST)
291 return "POWER ON RESET";
292 else if (cause & SRC_SRSR_WDOG_A5)
293 return "WDOG A5";
294 else if (cause & SRC_SRSR_WDOG_M4)
295 return "WDOG M4";
296 else if (cause & SRC_SRSR_JTAG_RST)
297 return "JTAG HIGH-Z";
298 else if (cause & SRC_SRSR_SW_RST)
299 return "SW RESET";
300 else if (cause & SRC_SRSR_RESETB)
301 return "EXTERNAL RESET";
302 else
303 return "unknown reset";
304 }
305
print_cpuinfo(void)306 int print_cpuinfo(void)
307 {
308 printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
309 soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
310 printf("Reset cause: %s\n", get_reset_cause());
311
312 return 0;
313 }
314 #endif
315
arch_cpu_init(void)316 int arch_cpu_init(void)
317 {
318 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
319
320 soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
321 soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
322
323 return 0;
324 }
325
326 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)327 int arch_misc_init(void)
328 {
329 char soc[6];
330
331 strcpy(soc, "vf");
332 strcat(soc, soc_type);
333 env_set("soc", soc);
334
335 return 0;
336 }
337 #endif
338
cpu_eth_init(bd_t * bis)339 int cpu_eth_init(bd_t *bis)
340 {
341 int rc = -ENODEV;
342
343 #if defined(CONFIG_FEC_MXC)
344 rc = fecmxc_initialize(bis);
345 #endif
346
347 return rc;
348 }
349
350 #ifdef CONFIG_FSL_ESDHC_IMX
cpu_mmc_init(bd_t * bis)351 int cpu_mmc_init(bd_t *bis)
352 {
353 return fsl_esdhc_mmc_init(bis);
354 }
355 #endif
356
get_clocks(void)357 int get_clocks(void)
358 {
359 #ifdef CONFIG_FSL_ESDHC_IMX
360 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
361 #endif
362 return 0;
363 }
364
365 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
enable_caches(void)366 void enable_caches(void)
367 {
368 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
369 enum dcache_option option = DCACHE_WRITETHROUGH;
370 #else
371 enum dcache_option option = DCACHE_WRITEBACK;
372 #endif
373 dcache_enable();
374 icache_enable();
375
376 /* Enable caching on OCRAM */
377 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
378 }
379 #endif
380
381 #ifdef CONFIG_SYS_I2C_MXC
382 /* i2c_num can be from 0 - 3 */
enable_i2c_clk(unsigned char enable,unsigned int i2c_num)383 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
384 {
385 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
386
387 switch (i2c_num) {
388 case 0:
389 clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
390 CCM_CCGR4_I2C0_CTRL_MASK);
391 case 2:
392 clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
393 CCM_CCGR10_I2C2_CTRL_MASK);
394 break;
395 default:
396 return -EINVAL;
397 }
398
399 return 0;
400 }
401 #endif
402