1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_B4420QDS 28 bool "Support B4420QDS" 29 select ARCH_B4420 30 select SUPPORT_SPL 31 select PHYS_64BIT 32 imply PANIC_HANG 33 34config TARGET_B4860QDS 35 bool "Support B4860QDS" 36 select ARCH_B4860 37 select BOARD_LATE_INIT if CHAIN_OF_TRUST 38 select SUPPORT_SPL 39 select PHYS_64BIT 40 select FSL_DDR_INTERACTIVE if !SPL_BUILD 41 imply PANIC_HANG 42 43config TARGET_BSC9131RDB 44 bool "Support BSC9131RDB" 45 select ARCH_BSC9131 46 select SUPPORT_SPL 47 select BOARD_EARLY_INIT_F 48 49config TARGET_BSC9132QDS 50 bool "Support BSC9132QDS" 51 select ARCH_BSC9132 52 select BOARD_LATE_INIT if CHAIN_OF_TRUST 53 select SUPPORT_SPL 54 select BOARD_EARLY_INIT_F 55 select FSL_DDR_INTERACTIVE 56 57config TARGET_C29XPCIE 58 bool "Support C29XPCIE" 59 select ARCH_C29X 60 select BOARD_LATE_INIT if CHAIN_OF_TRUST 61 select SUPPORT_SPL 62 select SUPPORT_TPL 63 select PHYS_64BIT 64 imply PANIC_HANG 65 66config TARGET_P3041DS 67 bool "Support P3041DS" 68 select PHYS_64BIT 69 select ARCH_P3041 70 select BOARD_LATE_INIT if CHAIN_OF_TRUST 71 imply CMD_SATA 72 imply PANIC_HANG 73 74config TARGET_P4080DS 75 bool "Support P4080DS" 76 select PHYS_64BIT 77 select ARCH_P4080 78 select BOARD_LATE_INIT if CHAIN_OF_TRUST 79 imply CMD_SATA 80 imply PANIC_HANG 81 82config TARGET_P5020DS 83 bool "Support P5020DS" 84 select PHYS_64BIT 85 select ARCH_P5020 86 select BOARD_LATE_INIT if CHAIN_OF_TRUST 87 imply CMD_SATA 88 imply PANIC_HANG 89 90config TARGET_P5040DS 91 bool "Support P5040DS" 92 select PHYS_64BIT 93 select ARCH_P5040 94 select BOARD_LATE_INIT if CHAIN_OF_TRUST 95 imply CMD_SATA 96 imply PANIC_HANG 97 98config TARGET_MPC8536DS 99 bool "Support MPC8536DS" 100 select ARCH_MPC8536 101# Use DDR3 controller with DDR2 DIMMs on this board 102 select SYS_FSL_DDRC_GEN3 103 imply CMD_SATA 104 imply FSL_SATA 105 106config TARGET_MPC8541CDS 107 bool "Support MPC8541CDS" 108 select ARCH_MPC8541 109 110config TARGET_MPC8544DS 111 bool "Support MPC8544DS" 112 select ARCH_MPC8544 113 imply PANIC_HANG 114 115config TARGET_MPC8548CDS 116 bool "Support MPC8548CDS" 117 select ARCH_MPC8548 118 119config TARGET_MPC8555CDS 120 bool "Support MPC8555CDS" 121 select ARCH_MPC8555 122 123config TARGET_MPC8568MDS 124 bool "Support MPC8568MDS" 125 select ARCH_MPC8568 126 127config TARGET_MPC8569MDS 128 bool "Support MPC8569MDS" 129 select ARCH_MPC8569 130 131config TARGET_MPC8572DS 132 bool "Support MPC8572DS" 133 select ARCH_MPC8572 134# Use DDR3 controller with DDR2 DIMMs on this board 135 select SYS_FSL_DDRC_GEN3 136 imply SCSI 137 imply PANIC_HANG 138 139config TARGET_P1010RDB_PA 140 bool "Support P1010RDB_PA" 141 select ARCH_P1010 142 select BOARD_LATE_INIT if CHAIN_OF_TRUST 143 select SUPPORT_SPL 144 select SUPPORT_TPL 145 imply CMD_EEPROM 146 imply CMD_SATA 147 imply PANIC_HANG 148 149config TARGET_P1010RDB_PB 150 bool "Support P1010RDB_PB" 151 select ARCH_P1010 152 select BOARD_LATE_INIT if CHAIN_OF_TRUST 153 select SUPPORT_SPL 154 select SUPPORT_TPL 155 imply CMD_EEPROM 156 imply CMD_SATA 157 imply PANIC_HANG 158 159config TARGET_P1022DS 160 bool "Support P1022DS" 161 select ARCH_P1022 162 select SUPPORT_SPL 163 select SUPPORT_TPL 164 imply CMD_SATA 165 imply FSL_SATA 166 167config TARGET_P1023RDB 168 bool "Support P1023RDB" 169 select ARCH_P1023 170 select FSL_DDR_INTERACTIVE 171 imply CMD_EEPROM 172 imply PANIC_HANG 173 174config TARGET_P1020MBG 175 bool "Support P1020MBG-PC" 176 select SUPPORT_SPL 177 select SUPPORT_TPL 178 select ARCH_P1020 179 imply CMD_EEPROM 180 imply CMD_SATA 181 imply PANIC_HANG 182 183config TARGET_P1020RDB_PC 184 bool "Support P1020RDB-PC" 185 select SUPPORT_SPL 186 select SUPPORT_TPL 187 select ARCH_P1020 188 imply CMD_EEPROM 189 imply CMD_SATA 190 imply PANIC_HANG 191 192config TARGET_P1020RDB_PD 193 bool "Support P1020RDB-PD" 194 select SUPPORT_SPL 195 select SUPPORT_TPL 196 select ARCH_P1020 197 imply CMD_EEPROM 198 imply CMD_SATA 199 imply PANIC_HANG 200 201config TARGET_P1020UTM 202 bool "Support P1020UTM" 203 select SUPPORT_SPL 204 select SUPPORT_TPL 205 select ARCH_P1020 206 imply CMD_EEPROM 207 imply CMD_SATA 208 imply PANIC_HANG 209 210config TARGET_P1021RDB 211 bool "Support P1021RDB" 212 select SUPPORT_SPL 213 select SUPPORT_TPL 214 select ARCH_P1021 215 imply CMD_EEPROM 216 imply CMD_SATA 217 imply PANIC_HANG 218 219config TARGET_P1024RDB 220 bool "Support P1024RDB" 221 select SUPPORT_SPL 222 select SUPPORT_TPL 223 select ARCH_P1024 224 imply CMD_EEPROM 225 imply CMD_SATA 226 imply PANIC_HANG 227 228config TARGET_P1025RDB 229 bool "Support P1025RDB" 230 select SUPPORT_SPL 231 select SUPPORT_TPL 232 select ARCH_P1025 233 imply CMD_EEPROM 234 imply CMD_SATA 235 imply SATA_SIL 236 237config TARGET_P2020RDB 238 bool "Support P2020RDB-PC" 239 select SUPPORT_SPL 240 select SUPPORT_TPL 241 select ARCH_P2020 242 imply CMD_EEPROM 243 imply CMD_SATA 244 imply SATA_SIL 245 246config TARGET_P1_TWR 247 bool "Support p1_twr" 248 select ARCH_P1025 249 250config TARGET_P2041RDB 251 bool "Support P2041RDB" 252 select ARCH_P2041 253 select BOARD_LATE_INIT if CHAIN_OF_TRUST 254 select PHYS_64BIT 255 imply CMD_SATA 256 imply FSL_SATA 257 258config TARGET_QEMU_PPCE500 259 bool "Support qemu-ppce500" 260 select ARCH_QEMU_E500 261 select PHYS_64BIT 262 263config TARGET_T1024QDS 264 bool "Support T1024QDS" 265 select ARCH_T1024 266 select BOARD_LATE_INIT if CHAIN_OF_TRUST 267 select SUPPORT_SPL 268 select PHYS_64BIT 269 imply CMD_EEPROM 270 imply CMD_SATA 271 imply FSL_SATA 272 273config TARGET_T1023RDB 274 bool "Support T1023RDB" 275 select ARCH_T1023 276 select BOARD_LATE_INIT if CHAIN_OF_TRUST 277 select SUPPORT_SPL 278 select PHYS_64BIT 279 select FSL_DDR_INTERACTIVE 280 imply CMD_EEPROM 281 imply PANIC_HANG 282 283config TARGET_T1024RDB 284 bool "Support T1024RDB" 285 select ARCH_T1024 286 select BOARD_LATE_INIT if CHAIN_OF_TRUST 287 select SUPPORT_SPL 288 select PHYS_64BIT 289 select FSL_DDR_INTERACTIVE 290 imply CMD_EEPROM 291 imply PANIC_HANG 292 293config TARGET_T1040QDS 294 bool "Support T1040QDS" 295 select ARCH_T1040 296 select BOARD_LATE_INIT if CHAIN_OF_TRUST 297 select PHYS_64BIT 298 select FSL_DDR_INTERACTIVE 299 imply CMD_EEPROM 300 imply CMD_SATA 301 imply PANIC_HANG 302 303config TARGET_T1040RDB 304 bool "Support T1040RDB" 305 select ARCH_T1040 306 select BOARD_LATE_INIT if CHAIN_OF_TRUST 307 select SUPPORT_SPL 308 select PHYS_64BIT 309 imply CMD_SATA 310 imply PANIC_HANG 311 312config TARGET_T1040D4RDB 313 bool "Support T1040D4RDB" 314 select ARCH_T1040 315 select BOARD_LATE_INIT if CHAIN_OF_TRUST 316 select SUPPORT_SPL 317 select PHYS_64BIT 318 imply CMD_SATA 319 imply PANIC_HANG 320 321config TARGET_T1042RDB 322 bool "Support T1042RDB" 323 select ARCH_T1042 324 select BOARD_LATE_INIT if CHAIN_OF_TRUST 325 select SUPPORT_SPL 326 select PHYS_64BIT 327 imply CMD_SATA 328 329config TARGET_T1042D4RDB 330 bool "Support T1042D4RDB" 331 select ARCH_T1042 332 select BOARD_LATE_INIT if CHAIN_OF_TRUST 333 select SUPPORT_SPL 334 select PHYS_64BIT 335 imply CMD_SATA 336 imply PANIC_HANG 337 338config TARGET_T1042RDB_PI 339 bool "Support T1042RDB_PI" 340 select ARCH_T1042 341 select BOARD_LATE_INIT if CHAIN_OF_TRUST 342 select SUPPORT_SPL 343 select PHYS_64BIT 344 imply CMD_SATA 345 imply PANIC_HANG 346 347config TARGET_T2080QDS 348 bool "Support T2080QDS" 349 select ARCH_T2080 350 select BOARD_LATE_INIT if CHAIN_OF_TRUST 351 select SUPPORT_SPL 352 select PHYS_64BIT 353 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 354 select FSL_DDR_INTERACTIVE 355 356config TARGET_T2080RDB 357 bool "Support T2080RDB" 358 select ARCH_T2080 359 select BOARD_LATE_INIT if CHAIN_OF_TRUST 360 select SUPPORT_SPL 361 select PHYS_64BIT 362 imply CMD_SATA 363 imply FSL_SATA 364 imply PANIC_HANG 365 366config TARGET_T2081QDS 367 bool "Support T2081QDS" 368 select ARCH_T2081 369 select SUPPORT_SPL 370 select PHYS_64BIT 371 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 372 select FSL_DDR_INTERACTIVE 373 374config TARGET_T4160QDS 375 bool "Support T4160QDS" 376 select ARCH_T4160 377 select BOARD_LATE_INIT if CHAIN_OF_TRUST 378 select SUPPORT_SPL 379 select PHYS_64BIT 380 imply CMD_SATA 381 imply PANIC_HANG 382 383config TARGET_T4160RDB 384 bool "Support T4160RDB" 385 select ARCH_T4160 386 select SUPPORT_SPL 387 select PHYS_64BIT 388 imply PANIC_HANG 389 390config TARGET_T4240QDS 391 bool "Support T4240QDS" 392 select ARCH_T4240 393 select BOARD_LATE_INIT if CHAIN_OF_TRUST 394 select SUPPORT_SPL 395 select PHYS_64BIT 396 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 397 imply CMD_SATA 398 imply PANIC_HANG 399 400config TARGET_T4240RDB 401 bool "Support T4240RDB" 402 select ARCH_T4240 403 select SUPPORT_SPL 404 select PHYS_64BIT 405 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 406 imply CMD_SATA 407 imply PANIC_HANG 408 409config TARGET_CONTROLCENTERD 410 bool "Support controlcenterd" 411 select ARCH_P1022 412 413config TARGET_KMP204X 414 bool "Support kmp204x" 415 select VENDOR_KM 416 417config TARGET_XPEDITE520X 418 bool "Support xpedite520x" 419 select ARCH_MPC8548 420 421config TARGET_XPEDITE537X 422 bool "Support xpedite537x" 423 select ARCH_MPC8572 424# Use DDR3 controller with DDR2 DIMMs on this board 425 select SYS_FSL_DDRC_GEN3 426 427config TARGET_XPEDITE550X 428 bool "Support xpedite550x" 429 select ARCH_P2020 430 431config TARGET_UCP1020 432 bool "Support uCP1020" 433 select ARCH_P1020 434 imply CMD_SATA 435 imply PANIC_HANG 436 437config TARGET_CYRUS_P5020 438 bool "Support Varisys Cyrus P5020" 439 select ARCH_P5020 440 select PHYS_64BIT 441 imply PANIC_HANG 442 443config TARGET_CYRUS_P5040 444 bool "Support Varisys Cyrus P5040" 445 select ARCH_P5040 446 select PHYS_64BIT 447 imply PANIC_HANG 448 449endchoice 450 451config ARCH_B4420 452 bool 453 select E500MC 454 select E6500 455 select FSL_LAW 456 select SYS_FSL_DDR_VER_47 457 select SYS_FSL_ERRATUM_A004477 458 select SYS_FSL_ERRATUM_A005871 459 select SYS_FSL_ERRATUM_A006379 460 select SYS_FSL_ERRATUM_A006384 461 select SYS_FSL_ERRATUM_A006475 462 select SYS_FSL_ERRATUM_A006593 463 select SYS_FSL_ERRATUM_A007075 464 select SYS_FSL_ERRATUM_A007186 465 select SYS_FSL_ERRATUM_A007212 466 select SYS_FSL_ERRATUM_A009942 467 select SYS_FSL_HAS_DDR3 468 select SYS_FSL_HAS_SEC 469 select SYS_FSL_QORIQ_CHASSIS2 470 select SYS_FSL_SEC_BE 471 select SYS_FSL_SEC_COMPAT_4 472 select SYS_PPC64 473 select FSL_IFC 474 imply CMD_EEPROM 475 imply CMD_NAND 476 imply CMD_REGINFO 477 478config ARCH_B4860 479 bool 480 select E500MC 481 select E6500 482 select FSL_LAW 483 select SYS_FSL_DDR_VER_47 484 select SYS_FSL_ERRATUM_A004477 485 select SYS_FSL_ERRATUM_A005871 486 select SYS_FSL_ERRATUM_A006379 487 select SYS_FSL_ERRATUM_A006384 488 select SYS_FSL_ERRATUM_A006475 489 select SYS_FSL_ERRATUM_A006593 490 select SYS_FSL_ERRATUM_A007075 491 select SYS_FSL_ERRATUM_A007186 492 select SYS_FSL_ERRATUM_A007212 493 select SYS_FSL_ERRATUM_A007907 494 select SYS_FSL_ERRATUM_A009942 495 select SYS_FSL_HAS_DDR3 496 select SYS_FSL_HAS_SEC 497 select SYS_FSL_QORIQ_CHASSIS2 498 select SYS_FSL_SEC_BE 499 select SYS_FSL_SEC_COMPAT_4 500 select SYS_PPC64 501 select FSL_IFC 502 imply CMD_EEPROM 503 imply CMD_NAND 504 imply CMD_REGINFO 505 506config ARCH_BSC9131 507 bool 508 select FSL_LAW 509 select SYS_FSL_DDR_VER_44 510 select SYS_FSL_ERRATUM_A004477 511 select SYS_FSL_ERRATUM_A005125 512 select SYS_FSL_ERRATUM_ESDHC111 513 select SYS_FSL_HAS_DDR3 514 select SYS_FSL_HAS_SEC 515 select SYS_FSL_SEC_BE 516 select SYS_FSL_SEC_COMPAT_4 517 select FSL_IFC 518 imply CMD_EEPROM 519 imply CMD_NAND 520 imply CMD_REGINFO 521 522config ARCH_BSC9132 523 bool 524 select FSL_LAW 525 select SYS_FSL_DDR_VER_46 526 select SYS_FSL_ERRATUM_A004477 527 select SYS_FSL_ERRATUM_A005125 528 select SYS_FSL_ERRATUM_A005434 529 select SYS_FSL_ERRATUM_ESDHC111 530 select SYS_FSL_ERRATUM_I2C_A004447 531 select SYS_FSL_ERRATUM_IFC_A002769 532 select FSL_PCIE_RESET 533 select SYS_FSL_HAS_DDR3 534 select SYS_FSL_HAS_SEC 535 select SYS_FSL_SEC_BE 536 select SYS_FSL_SEC_COMPAT_4 537 select SYS_PPC_E500_USE_DEBUG_TLB 538 select FSL_IFC 539 imply CMD_EEPROM 540 imply CMD_MTDPARTS 541 imply CMD_NAND 542 imply CMD_PCI 543 imply CMD_REGINFO 544 545config ARCH_C29X 546 bool 547 select FSL_LAW 548 select SYS_FSL_DDR_VER_46 549 select SYS_FSL_ERRATUM_A005125 550 select SYS_FSL_ERRATUM_ESDHC111 551 select FSL_PCIE_RESET 552 select SYS_FSL_HAS_DDR3 553 select SYS_FSL_HAS_SEC 554 select SYS_FSL_SEC_BE 555 select SYS_FSL_SEC_COMPAT_6 556 select SYS_PPC_E500_USE_DEBUG_TLB 557 select FSL_IFC 558 imply CMD_NAND 559 imply CMD_PCI 560 imply CMD_REGINFO 561 562config ARCH_MPC8536 563 bool 564 select FSL_LAW 565 select SYS_FSL_ERRATUM_A004508 566 select SYS_FSL_ERRATUM_A005125 567 select FSL_PCIE_RESET 568 select SYS_FSL_HAS_DDR2 569 select SYS_FSL_HAS_DDR3 570 select SYS_FSL_HAS_SEC 571 select SYS_FSL_SEC_BE 572 select SYS_FSL_SEC_COMPAT_2 573 select SYS_PPC_E500_USE_DEBUG_TLB 574 select FSL_ELBC 575 imply CMD_NAND 576 imply CMD_SATA 577 imply CMD_REGINFO 578 579config ARCH_MPC8540 580 bool 581 select FSL_LAW 582 select SYS_FSL_HAS_DDR1 583 584config ARCH_MPC8541 585 bool 586 select FSL_LAW 587 select SYS_FSL_HAS_DDR1 588 select SYS_FSL_HAS_SEC 589 select SYS_FSL_SEC_BE 590 select SYS_FSL_SEC_COMPAT_2 591 592config ARCH_MPC8544 593 bool 594 select FSL_LAW 595 select SYS_FSL_ERRATUM_A005125 596 select FSL_PCIE_RESET 597 select SYS_FSL_HAS_DDR2 598 select SYS_FSL_HAS_SEC 599 select SYS_FSL_SEC_BE 600 select SYS_FSL_SEC_COMPAT_2 601 select SYS_PPC_E500_USE_DEBUG_TLB 602 select FSL_ELBC 603 604config ARCH_MPC8548 605 bool 606 select FSL_LAW 607 select SYS_FSL_ERRATUM_A005125 608 select SYS_FSL_ERRATUM_NMG_DDR120 609 select SYS_FSL_ERRATUM_NMG_LBC103 610 select SYS_FSL_ERRATUM_NMG_ETSEC129 611 select SYS_FSL_ERRATUM_I2C_A004447 612 select FSL_PCIE_RESET 613 select SYS_FSL_HAS_DDR2 614 select SYS_FSL_HAS_DDR1 615 select SYS_FSL_HAS_SEC 616 select SYS_FSL_SEC_BE 617 select SYS_FSL_SEC_COMPAT_2 618 select SYS_PPC_E500_USE_DEBUG_TLB 619 imply CMD_REGINFO 620 621config ARCH_MPC8555 622 bool 623 select FSL_LAW 624 select SYS_FSL_HAS_DDR1 625 select SYS_FSL_HAS_SEC 626 select SYS_FSL_SEC_BE 627 select SYS_FSL_SEC_COMPAT_2 628 629config ARCH_MPC8560 630 bool 631 select FSL_LAW 632 select SYS_FSL_HAS_DDR1 633 634config ARCH_MPC8568 635 bool 636 select FSL_LAW 637 select FSL_PCIE_RESET 638 select SYS_FSL_HAS_DDR2 639 select SYS_FSL_HAS_SEC 640 select SYS_FSL_SEC_BE 641 select SYS_FSL_SEC_COMPAT_2 642 643config ARCH_MPC8569 644 bool 645 select FSL_LAW 646 select SYS_FSL_ERRATUM_A004508 647 select SYS_FSL_ERRATUM_A005125 648 select FSL_PCIE_RESET 649 select SYS_FSL_HAS_DDR3 650 select SYS_FSL_HAS_SEC 651 select SYS_FSL_SEC_BE 652 select SYS_FSL_SEC_COMPAT_2 653 select FSL_ELBC 654 imply CMD_NAND 655 656config ARCH_MPC8572 657 bool 658 select FSL_LAW 659 select SYS_FSL_ERRATUM_A004508 660 select SYS_FSL_ERRATUM_A005125 661 select SYS_FSL_ERRATUM_DDR_115 662 select SYS_FSL_ERRATUM_DDR111_DDR134 663 select FSL_PCIE_RESET 664 select SYS_FSL_HAS_DDR2 665 select SYS_FSL_HAS_DDR3 666 select SYS_FSL_HAS_SEC 667 select SYS_FSL_SEC_BE 668 select SYS_FSL_SEC_COMPAT_2 669 select SYS_PPC_E500_USE_DEBUG_TLB 670 select FSL_ELBC 671 imply CMD_NAND 672 673config ARCH_P1010 674 bool 675 select FSL_LAW 676 select SYS_FSL_ERRATUM_A004477 677 select SYS_FSL_ERRATUM_A004508 678 select SYS_FSL_ERRATUM_A005125 679 select SYS_FSL_ERRATUM_A005275 680 select SYS_FSL_ERRATUM_A006261 681 select SYS_FSL_ERRATUM_A007075 682 select SYS_FSL_ERRATUM_ESDHC111 683 select SYS_FSL_ERRATUM_I2C_A004447 684 select SYS_FSL_ERRATUM_IFC_A002769 685 select SYS_FSL_ERRATUM_P1010_A003549 686 select SYS_FSL_ERRATUM_SEC_A003571 687 select SYS_FSL_ERRATUM_IFC_A003399 688 select FSL_PCIE_RESET 689 select SYS_FSL_HAS_DDR3 690 select SYS_FSL_HAS_SEC 691 select SYS_FSL_SEC_BE 692 select SYS_FSL_SEC_COMPAT_4 693 select SYS_PPC_E500_USE_DEBUG_TLB 694 select FSL_IFC 695 imply CMD_EEPROM 696 imply CMD_MTDPARTS 697 imply CMD_NAND 698 imply CMD_SATA 699 imply CMD_PCI 700 imply CMD_REGINFO 701 imply FSL_SATA 702 703config ARCH_P1011 704 bool 705 select FSL_LAW 706 select SYS_FSL_ERRATUM_A004508 707 select SYS_FSL_ERRATUM_A005125 708 select SYS_FSL_ERRATUM_ELBC_A001 709 select SYS_FSL_ERRATUM_ESDHC111 710 select FSL_PCIE_DISABLE_ASPM 711 select SYS_FSL_HAS_DDR3 712 select SYS_FSL_HAS_SEC 713 select SYS_FSL_SEC_BE 714 select SYS_FSL_SEC_COMPAT_2 715 select SYS_PPC_E500_USE_DEBUG_TLB 716 select FSL_ELBC 717 718config ARCH_P1020 719 bool 720 select FSL_LAW 721 select SYS_FSL_ERRATUM_A004508 722 select SYS_FSL_ERRATUM_A005125 723 select SYS_FSL_ERRATUM_ELBC_A001 724 select SYS_FSL_ERRATUM_ESDHC111 725 select FSL_PCIE_DISABLE_ASPM 726 select FSL_PCIE_RESET 727 select SYS_FSL_HAS_DDR3 728 select SYS_FSL_HAS_SEC 729 select SYS_FSL_SEC_BE 730 select SYS_FSL_SEC_COMPAT_2 731 select SYS_PPC_E500_USE_DEBUG_TLB 732 select FSL_ELBC 733 imply CMD_NAND 734 imply CMD_SATA 735 imply CMD_PCI 736 imply CMD_REGINFO 737 imply SATA_SIL 738 739config ARCH_P1021 740 bool 741 select FSL_LAW 742 select SYS_FSL_ERRATUM_A004508 743 select SYS_FSL_ERRATUM_A005125 744 select SYS_FSL_ERRATUM_ELBC_A001 745 select SYS_FSL_ERRATUM_ESDHC111 746 select FSL_PCIE_DISABLE_ASPM 747 select FSL_PCIE_RESET 748 select SYS_FSL_HAS_DDR3 749 select SYS_FSL_HAS_SEC 750 select SYS_FSL_SEC_BE 751 select SYS_FSL_SEC_COMPAT_2 752 select SYS_PPC_E500_USE_DEBUG_TLB 753 select FSL_ELBC 754 imply CMD_REGINFO 755 imply CMD_NAND 756 imply CMD_SATA 757 imply CMD_REGINFO 758 imply SATA_SIL 759 760config ARCH_P1022 761 bool 762 select FSL_LAW 763 select SYS_FSL_ERRATUM_A004477 764 select SYS_FSL_ERRATUM_A004508 765 select SYS_FSL_ERRATUM_A005125 766 select SYS_FSL_ERRATUM_ELBC_A001 767 select SYS_FSL_ERRATUM_ESDHC111 768 select SYS_FSL_ERRATUM_SATA_A001 769 select FSL_PCIE_RESET 770 select SYS_FSL_HAS_DDR3 771 select SYS_FSL_HAS_SEC 772 select SYS_FSL_SEC_BE 773 select SYS_FSL_SEC_COMPAT_2 774 select SYS_PPC_E500_USE_DEBUG_TLB 775 select FSL_ELBC 776 777config ARCH_P1023 778 bool 779 select FSL_LAW 780 select SYS_FSL_ERRATUM_A004508 781 select SYS_FSL_ERRATUM_A005125 782 select SYS_FSL_ERRATUM_I2C_A004447 783 select FSL_PCIE_RESET 784 select SYS_FSL_HAS_DDR3 785 select SYS_FSL_HAS_SEC 786 select SYS_FSL_SEC_BE 787 select SYS_FSL_SEC_COMPAT_4 788 select FSL_ELBC 789 790config ARCH_P1024 791 bool 792 select FSL_LAW 793 select SYS_FSL_ERRATUM_A004508 794 select SYS_FSL_ERRATUM_A005125 795 select SYS_FSL_ERRATUM_ELBC_A001 796 select SYS_FSL_ERRATUM_ESDHC111 797 select FSL_PCIE_DISABLE_ASPM 798 select FSL_PCIE_RESET 799 select SYS_FSL_HAS_DDR3 800 select SYS_FSL_HAS_SEC 801 select SYS_FSL_SEC_BE 802 select SYS_FSL_SEC_COMPAT_2 803 select SYS_PPC_E500_USE_DEBUG_TLB 804 select FSL_ELBC 805 imply CMD_EEPROM 806 imply CMD_NAND 807 imply CMD_SATA 808 imply CMD_PCI 809 imply CMD_REGINFO 810 imply SATA_SIL 811 812config ARCH_P1025 813 bool 814 select FSL_LAW 815 select SYS_FSL_ERRATUM_A004508 816 select SYS_FSL_ERRATUM_A005125 817 select SYS_FSL_ERRATUM_ELBC_A001 818 select SYS_FSL_ERRATUM_ESDHC111 819 select FSL_PCIE_DISABLE_ASPM 820 select FSL_PCIE_RESET 821 select SYS_FSL_HAS_DDR3 822 select SYS_FSL_HAS_SEC 823 select SYS_FSL_SEC_BE 824 select SYS_FSL_SEC_COMPAT_2 825 select SYS_PPC_E500_USE_DEBUG_TLB 826 select FSL_ELBC 827 imply CMD_SATA 828 imply CMD_REGINFO 829 830config ARCH_P2020 831 bool 832 select FSL_LAW 833 select SYS_FSL_ERRATUM_A004477 834 select SYS_FSL_ERRATUM_A004508 835 select SYS_FSL_ERRATUM_A005125 836 select SYS_FSL_ERRATUM_ESDHC111 837 select SYS_FSL_ERRATUM_ESDHC_A001 838 select FSL_PCIE_RESET 839 select SYS_FSL_HAS_DDR3 840 select SYS_FSL_HAS_SEC 841 select SYS_FSL_SEC_BE 842 select SYS_FSL_SEC_COMPAT_2 843 select SYS_PPC_E500_USE_DEBUG_TLB 844 select FSL_ELBC 845 imply CMD_EEPROM 846 imply CMD_NAND 847 imply CMD_REGINFO 848 849config ARCH_P2041 850 bool 851 select E500MC 852 select FSL_LAW 853 select SYS_FSL_ERRATUM_A004510 854 select SYS_FSL_ERRATUM_A004849 855 select SYS_FSL_ERRATUM_A005275 856 select SYS_FSL_ERRATUM_A006261 857 select SYS_FSL_ERRATUM_CPU_A003999 858 select SYS_FSL_ERRATUM_DDR_A003 859 select SYS_FSL_ERRATUM_DDR_A003474 860 select SYS_FSL_ERRATUM_ESDHC111 861 select SYS_FSL_ERRATUM_I2C_A004447 862 select SYS_FSL_ERRATUM_NMG_CPU_A011 863 select SYS_FSL_ERRATUM_SRIO_A004034 864 select SYS_FSL_ERRATUM_USB14 865 select SYS_FSL_HAS_DDR3 866 select SYS_FSL_HAS_SEC 867 select SYS_FSL_QORIQ_CHASSIS1 868 select SYS_FSL_SEC_BE 869 select SYS_FSL_SEC_COMPAT_4 870 select FSL_ELBC 871 imply CMD_NAND 872 873config ARCH_P3041 874 bool 875 select E500MC 876 select FSL_LAW 877 select SYS_FSL_DDR_VER_44 878 select SYS_FSL_ERRATUM_A004510 879 select SYS_FSL_ERRATUM_A004849 880 select SYS_FSL_ERRATUM_A005275 881 select SYS_FSL_ERRATUM_A005812 882 select SYS_FSL_ERRATUM_A006261 883 select SYS_FSL_ERRATUM_CPU_A003999 884 select SYS_FSL_ERRATUM_DDR_A003 885 select SYS_FSL_ERRATUM_DDR_A003474 886 select SYS_FSL_ERRATUM_ESDHC111 887 select SYS_FSL_ERRATUM_I2C_A004447 888 select SYS_FSL_ERRATUM_NMG_CPU_A011 889 select SYS_FSL_ERRATUM_SRIO_A004034 890 select SYS_FSL_ERRATUM_USB14 891 select SYS_FSL_HAS_DDR3 892 select SYS_FSL_HAS_SEC 893 select SYS_FSL_QORIQ_CHASSIS1 894 select SYS_FSL_SEC_BE 895 select SYS_FSL_SEC_COMPAT_4 896 select FSL_ELBC 897 imply CMD_NAND 898 imply CMD_SATA 899 imply CMD_REGINFO 900 imply FSL_SATA 901 902config ARCH_P4080 903 bool 904 select E500MC 905 select FSL_LAW 906 select SYS_FSL_DDR_VER_44 907 select SYS_FSL_ERRATUM_A004510 908 select SYS_FSL_ERRATUM_A004580 909 select SYS_FSL_ERRATUM_A004849 910 select SYS_FSL_ERRATUM_A005812 911 select SYS_FSL_ERRATUM_A007075 912 select SYS_FSL_ERRATUM_CPC_A002 913 select SYS_FSL_ERRATUM_CPC_A003 914 select SYS_FSL_ERRATUM_CPU_A003999 915 select SYS_FSL_ERRATUM_DDR_A003 916 select SYS_FSL_ERRATUM_DDR_A003474 917 select SYS_FSL_ERRATUM_ELBC_A001 918 select SYS_FSL_ERRATUM_ESDHC111 919 select SYS_FSL_ERRATUM_ESDHC13 920 select SYS_FSL_ERRATUM_ESDHC135 921 select SYS_FSL_ERRATUM_I2C_A004447 922 select SYS_FSL_ERRATUM_NMG_CPU_A011 923 select SYS_FSL_ERRATUM_SRIO_A004034 924 select SYS_P4080_ERRATUM_CPU22 925 select SYS_P4080_ERRATUM_PCIE_A003 926 select SYS_P4080_ERRATUM_SERDES8 927 select SYS_P4080_ERRATUM_SERDES9 928 select SYS_P4080_ERRATUM_SERDES_A001 929 select SYS_P4080_ERRATUM_SERDES_A005 930 select SYS_FSL_HAS_DDR3 931 select SYS_FSL_HAS_SEC 932 select SYS_FSL_QORIQ_CHASSIS1 933 select SYS_FSL_SEC_BE 934 select SYS_FSL_SEC_COMPAT_4 935 select FSL_ELBC 936 imply CMD_SATA 937 imply CMD_REGINFO 938 imply SATA_SIL 939 940config ARCH_P5020 941 bool 942 select E500MC 943 select FSL_LAW 944 select SYS_FSL_DDR_VER_44 945 select SYS_FSL_ERRATUM_A004510 946 select SYS_FSL_ERRATUM_A005275 947 select SYS_FSL_ERRATUM_A006261 948 select SYS_FSL_ERRATUM_DDR_A003 949 select SYS_FSL_ERRATUM_DDR_A003474 950 select SYS_FSL_ERRATUM_ESDHC111 951 select SYS_FSL_ERRATUM_I2C_A004447 952 select SYS_FSL_ERRATUM_SRIO_A004034 953 select SYS_FSL_ERRATUM_USB14 954 select SYS_FSL_HAS_DDR3 955 select SYS_FSL_HAS_SEC 956 select SYS_FSL_QORIQ_CHASSIS1 957 select SYS_FSL_SEC_BE 958 select SYS_FSL_SEC_COMPAT_4 959 select SYS_PPC64 960 select FSL_ELBC 961 imply CMD_SATA 962 imply CMD_REGINFO 963 imply FSL_SATA 964 965config ARCH_P5040 966 bool 967 select E500MC 968 select FSL_LAW 969 select SYS_FSL_DDR_VER_44 970 select SYS_FSL_ERRATUM_A004510 971 select SYS_FSL_ERRATUM_A004699 972 select SYS_FSL_ERRATUM_A005275 973 select SYS_FSL_ERRATUM_A005812 974 select SYS_FSL_ERRATUM_A006261 975 select SYS_FSL_ERRATUM_DDR_A003 976 select SYS_FSL_ERRATUM_DDR_A003474 977 select SYS_FSL_ERRATUM_ESDHC111 978 select SYS_FSL_ERRATUM_USB14 979 select SYS_FSL_HAS_DDR3 980 select SYS_FSL_HAS_SEC 981 select SYS_FSL_QORIQ_CHASSIS1 982 select SYS_FSL_SEC_BE 983 select SYS_FSL_SEC_COMPAT_4 984 select SYS_PPC64 985 select FSL_ELBC 986 imply CMD_SATA 987 imply CMD_REGINFO 988 imply FSL_SATA 989 990config ARCH_QEMU_E500 991 bool 992 993config ARCH_T1023 994 bool 995 select E500MC 996 select FSL_LAW 997 select SYS_FSL_DDR_VER_50 998 select SYS_FSL_ERRATUM_A008378 999 select SYS_FSL_ERRATUM_A009663 1000 select SYS_FSL_ERRATUM_A009942 1001 select SYS_FSL_ERRATUM_ESDHC111 1002 select SYS_FSL_HAS_DDR3 1003 select SYS_FSL_HAS_DDR4 1004 select SYS_FSL_HAS_SEC 1005 select SYS_FSL_QORIQ_CHASSIS2 1006 select SYS_FSL_SEC_BE 1007 select SYS_FSL_SEC_COMPAT_5 1008 select FSL_IFC 1009 imply CMD_EEPROM 1010 imply CMD_NAND 1011 imply CMD_REGINFO 1012 1013config ARCH_T1024 1014 bool 1015 select E500MC 1016 select FSL_LAW 1017 select SYS_FSL_DDR_VER_50 1018 select SYS_FSL_ERRATUM_A008378 1019 select SYS_FSL_ERRATUM_A009663 1020 select SYS_FSL_ERRATUM_A009942 1021 select SYS_FSL_ERRATUM_ESDHC111 1022 select SYS_FSL_HAS_DDR3 1023 select SYS_FSL_HAS_DDR4 1024 select SYS_FSL_HAS_SEC 1025 select SYS_FSL_QORIQ_CHASSIS2 1026 select SYS_FSL_SEC_BE 1027 select SYS_FSL_SEC_COMPAT_5 1028 select FSL_IFC 1029 imply CMD_EEPROM 1030 imply CMD_NAND 1031 imply CMD_MTDPARTS 1032 imply CMD_REGINFO 1033 1034config ARCH_T1040 1035 bool 1036 select E500MC 1037 select FSL_LAW 1038 select SYS_FSL_DDR_VER_50 1039 select SYS_FSL_ERRATUM_A008044 1040 select SYS_FSL_ERRATUM_A008378 1041 select SYS_FSL_ERRATUM_A009663 1042 select SYS_FSL_ERRATUM_A009942 1043 select SYS_FSL_ERRATUM_ESDHC111 1044 select SYS_FSL_HAS_DDR3 1045 select SYS_FSL_HAS_DDR4 1046 select SYS_FSL_HAS_SEC 1047 select SYS_FSL_QORIQ_CHASSIS2 1048 select SYS_FSL_SEC_BE 1049 select SYS_FSL_SEC_COMPAT_5 1050 select FSL_IFC 1051 imply CMD_MTDPARTS 1052 imply CMD_NAND 1053 imply CMD_SATA 1054 imply CMD_REGINFO 1055 imply FSL_SATA 1056 1057config ARCH_T1042 1058 bool 1059 select E500MC 1060 select FSL_LAW 1061 select SYS_FSL_DDR_VER_50 1062 select SYS_FSL_ERRATUM_A008044 1063 select SYS_FSL_ERRATUM_A008378 1064 select SYS_FSL_ERRATUM_A009663 1065 select SYS_FSL_ERRATUM_A009942 1066 select SYS_FSL_ERRATUM_ESDHC111 1067 select SYS_FSL_HAS_DDR3 1068 select SYS_FSL_HAS_DDR4 1069 select SYS_FSL_HAS_SEC 1070 select SYS_FSL_QORIQ_CHASSIS2 1071 select SYS_FSL_SEC_BE 1072 select SYS_FSL_SEC_COMPAT_5 1073 select FSL_IFC 1074 imply CMD_MTDPARTS 1075 imply CMD_NAND 1076 imply CMD_SATA 1077 imply CMD_REGINFO 1078 imply FSL_SATA 1079 1080config ARCH_T2080 1081 bool 1082 select E500MC 1083 select E6500 1084 select FSL_LAW 1085 select SYS_FSL_DDR_VER_47 1086 select SYS_FSL_ERRATUM_A006379 1087 select SYS_FSL_ERRATUM_A006593 1088 select SYS_FSL_ERRATUM_A007186 1089 select SYS_FSL_ERRATUM_A007212 1090 select SYS_FSL_ERRATUM_A007815 1091 select SYS_FSL_ERRATUM_A007907 1092 select SYS_FSL_ERRATUM_A009942 1093 select SYS_FSL_ERRATUM_ESDHC111 1094 select FSL_PCIE_RESET 1095 select SYS_FSL_HAS_DDR3 1096 select SYS_FSL_HAS_SEC 1097 select SYS_FSL_QORIQ_CHASSIS2 1098 select SYS_FSL_SEC_BE 1099 select SYS_FSL_SEC_COMPAT_4 1100 select SYS_PPC64 1101 select FSL_IFC 1102 imply CMD_NAND 1103 imply CMD_REGINFO 1104 1105config ARCH_T2081 1106 bool 1107 select E500MC 1108 select E6500 1109 select FSL_LAW 1110 select SYS_FSL_DDR_VER_47 1111 select SYS_FSL_ERRATUM_A006379 1112 select SYS_FSL_ERRATUM_A006593 1113 select SYS_FSL_ERRATUM_A007186 1114 select SYS_FSL_ERRATUM_A007212 1115 select SYS_FSL_ERRATUM_A009942 1116 select SYS_FSL_ERRATUM_ESDHC111 1117 select FSL_PCIE_RESET 1118 select SYS_FSL_HAS_DDR3 1119 select SYS_FSL_HAS_SEC 1120 select SYS_FSL_QORIQ_CHASSIS2 1121 select SYS_FSL_SEC_BE 1122 select SYS_FSL_SEC_COMPAT_4 1123 select SYS_PPC64 1124 select FSL_IFC 1125 imply CMD_NAND 1126 imply CMD_REGINFO 1127 1128config ARCH_T4160 1129 bool 1130 select E500MC 1131 select E6500 1132 select FSL_LAW 1133 select SYS_FSL_DDR_VER_47 1134 select SYS_FSL_ERRATUM_A004468 1135 select SYS_FSL_ERRATUM_A005871 1136 select SYS_FSL_ERRATUM_A006379 1137 select SYS_FSL_ERRATUM_A006593 1138 select SYS_FSL_ERRATUM_A007186 1139 select SYS_FSL_ERRATUM_A007798 1140 select SYS_FSL_ERRATUM_A009942 1141 select SYS_FSL_HAS_DDR3 1142 select SYS_FSL_HAS_SEC 1143 select SYS_FSL_QORIQ_CHASSIS2 1144 select SYS_FSL_SEC_BE 1145 select SYS_FSL_SEC_COMPAT_4 1146 select SYS_PPC64 1147 select FSL_IFC 1148 imply CMD_SATA 1149 imply CMD_NAND 1150 imply CMD_REGINFO 1151 imply FSL_SATA 1152 1153config ARCH_T4240 1154 bool 1155 select E500MC 1156 select E6500 1157 select FSL_LAW 1158 select SYS_FSL_DDR_VER_47 1159 select SYS_FSL_ERRATUM_A004468 1160 select SYS_FSL_ERRATUM_A005871 1161 select SYS_FSL_ERRATUM_A006261 1162 select SYS_FSL_ERRATUM_A006379 1163 select SYS_FSL_ERRATUM_A006593 1164 select SYS_FSL_ERRATUM_A007186 1165 select SYS_FSL_ERRATUM_A007798 1166 select SYS_FSL_ERRATUM_A007815 1167 select SYS_FSL_ERRATUM_A007907 1168 select SYS_FSL_ERRATUM_A009942 1169 select SYS_FSL_HAS_DDR3 1170 select SYS_FSL_HAS_SEC 1171 select SYS_FSL_QORIQ_CHASSIS2 1172 select SYS_FSL_SEC_BE 1173 select SYS_FSL_SEC_COMPAT_4 1174 select SYS_PPC64 1175 select FSL_IFC 1176 imply CMD_SATA 1177 imply CMD_NAND 1178 imply CMD_REGINFO 1179 imply FSL_SATA 1180 1181config MPC85XX_HAVE_RESET_VECTOR 1182 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" 1183 depends on MPC85xx 1184 1185config BOOKE 1186 bool 1187 default y 1188 1189config E500 1190 bool 1191 default y 1192 help 1193 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1194 1195config E500MC 1196 bool 1197 imply CMD_PCI 1198 help 1199 Enble PowerPC E500MC core 1200 1201config E6500 1202 bool 1203 help 1204 Enable PowerPC E6500 core 1205 1206config FSL_LAW 1207 bool 1208 help 1209 Use Freescale common code for Local Access Window 1210 1211config NXP_ESBC 1212 bool "NXP_ESBC" 1213 help 1214 Enable Freescale Secure Boot feature. Normally selected 1215 by defconfig. If unsure, do not change. 1216 1217config MAX_CPUS 1218 int "Maximum number of CPUs permitted for MPC85xx" 1219 default 12 if ARCH_T4240 1220 default 8 if ARCH_P4080 || \ 1221 ARCH_T4160 1222 default 4 if ARCH_B4860 || \ 1223 ARCH_P2041 || \ 1224 ARCH_P3041 || \ 1225 ARCH_P5040 || \ 1226 ARCH_T1040 || \ 1227 ARCH_T1042 || \ 1228 ARCH_T2080 || \ 1229 ARCH_T2081 1230 default 2 if ARCH_B4420 || \ 1231 ARCH_BSC9132 || \ 1232 ARCH_MPC8572 || \ 1233 ARCH_P1020 || \ 1234 ARCH_P1021 || \ 1235 ARCH_P1022 || \ 1236 ARCH_P1023 || \ 1237 ARCH_P1024 || \ 1238 ARCH_P1025 || \ 1239 ARCH_P2020 || \ 1240 ARCH_P5020 || \ 1241 ARCH_T1023 || \ 1242 ARCH_T1024 1243 default 1 1244 help 1245 Set this number to the maximum number of possible CPUs in the SoC. 1246 SoCs may have multiple clusters with each cluster may have multiple 1247 ports. If some ports are reserved but higher ports are used for 1248 cores, count the reserved ports. This will allocate enough memory 1249 in spin table to properly handle all cores. 1250 1251config SYS_CCSRBAR_DEFAULT 1252 hex "Default CCSRBAR address" 1253 default 0xff700000 if ARCH_BSC9131 || \ 1254 ARCH_BSC9132 || \ 1255 ARCH_C29X || \ 1256 ARCH_MPC8536 || \ 1257 ARCH_MPC8540 || \ 1258 ARCH_MPC8541 || \ 1259 ARCH_MPC8544 || \ 1260 ARCH_MPC8548 || \ 1261 ARCH_MPC8555 || \ 1262 ARCH_MPC8560 || \ 1263 ARCH_MPC8568 || \ 1264 ARCH_MPC8569 || \ 1265 ARCH_MPC8572 || \ 1266 ARCH_P1010 || \ 1267 ARCH_P1011 || \ 1268 ARCH_P1020 || \ 1269 ARCH_P1021 || \ 1270 ARCH_P1022 || \ 1271 ARCH_P1024 || \ 1272 ARCH_P1025 || \ 1273 ARCH_P2020 1274 default 0xff600000 if ARCH_P1023 1275 default 0xfe000000 if ARCH_B4420 || \ 1276 ARCH_B4860 || \ 1277 ARCH_P2041 || \ 1278 ARCH_P3041 || \ 1279 ARCH_P4080 || \ 1280 ARCH_P5020 || \ 1281 ARCH_P5040 || \ 1282 ARCH_T1023 || \ 1283 ARCH_T1024 || \ 1284 ARCH_T1040 || \ 1285 ARCH_T1042 || \ 1286 ARCH_T2080 || \ 1287 ARCH_T2081 || \ 1288 ARCH_T4160 || \ 1289 ARCH_T4240 1290 default 0xe0000000 if ARCH_QEMU_E500 1291 help 1292 Default value of CCSRBAR comes from power-on-reset. It 1293 is fixed on each SoC. Some SoCs can have different value 1294 if changed by pre-boot regime. The value here must match 1295 the current value in SoC. If not sure, do not change. 1296 1297config SYS_FSL_ERRATUM_A004468 1298 bool 1299 1300config SYS_FSL_ERRATUM_A004477 1301 bool 1302 1303config SYS_FSL_ERRATUM_A004508 1304 bool 1305 1306config SYS_FSL_ERRATUM_A004580 1307 bool 1308 1309config SYS_FSL_ERRATUM_A004699 1310 bool 1311 1312config SYS_FSL_ERRATUM_A004849 1313 bool 1314 1315config SYS_FSL_ERRATUM_A004510 1316 bool 1317 1318config SYS_FSL_ERRATUM_A004510_SVR_REV 1319 hex 1320 depends on SYS_FSL_ERRATUM_A004510 1321 default 0x20 if ARCH_P4080 1322 default 0x10 1323 1324config SYS_FSL_ERRATUM_A004510_SVR_REV2 1325 hex 1326 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1327 default 0x11 1328 1329config SYS_FSL_ERRATUM_A005125 1330 bool 1331 1332config SYS_FSL_ERRATUM_A005434 1333 bool 1334 1335config SYS_FSL_ERRATUM_A005812 1336 bool 1337 1338config SYS_FSL_ERRATUM_A005871 1339 bool 1340 1341config SYS_FSL_ERRATUM_A005275 1342 bool 1343 1344config SYS_FSL_ERRATUM_A006261 1345 bool 1346 1347config SYS_FSL_ERRATUM_A006379 1348 bool 1349 1350config SYS_FSL_ERRATUM_A006384 1351 bool 1352 1353config SYS_FSL_ERRATUM_A006475 1354 bool 1355 1356config SYS_FSL_ERRATUM_A006593 1357 bool 1358 1359config SYS_FSL_ERRATUM_A007075 1360 bool 1361 1362config SYS_FSL_ERRATUM_A007186 1363 bool 1364 1365config SYS_FSL_ERRATUM_A007212 1366 bool 1367 1368config SYS_FSL_ERRATUM_A007815 1369 bool 1370 1371config SYS_FSL_ERRATUM_A007798 1372 bool 1373 1374config SYS_FSL_ERRATUM_A007907 1375 bool 1376 1377config SYS_FSL_ERRATUM_A008044 1378 bool 1379 1380config SYS_FSL_ERRATUM_CPC_A002 1381 bool 1382 1383config SYS_FSL_ERRATUM_CPC_A003 1384 bool 1385 1386config SYS_FSL_ERRATUM_CPU_A003999 1387 bool 1388 1389config SYS_FSL_ERRATUM_ELBC_A001 1390 bool 1391 1392config SYS_FSL_ERRATUM_I2C_A004447 1393 bool 1394 1395config SYS_FSL_A004447_SVR_REV 1396 hex 1397 depends on SYS_FSL_ERRATUM_I2C_A004447 1398 default 0x00 if ARCH_MPC8548 1399 default 0x10 if ARCH_P1010 1400 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1401 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1402 1403config SYS_FSL_ERRATUM_IFC_A002769 1404 bool 1405 1406config SYS_FSL_ERRATUM_IFC_A003399 1407 bool 1408 1409config SYS_FSL_ERRATUM_NMG_CPU_A011 1410 bool 1411 1412config SYS_FSL_ERRATUM_NMG_ETSEC129 1413 bool 1414 1415config SYS_FSL_ERRATUM_NMG_LBC103 1416 bool 1417 1418config SYS_FSL_ERRATUM_P1010_A003549 1419 bool 1420 1421config SYS_FSL_ERRATUM_SATA_A001 1422 bool 1423 1424config SYS_FSL_ERRATUM_SEC_A003571 1425 bool 1426 1427config SYS_FSL_ERRATUM_SRIO_A004034 1428 bool 1429 1430config SYS_FSL_ERRATUM_USB14 1431 bool 1432 1433config SYS_P4080_ERRATUM_CPU22 1434 bool 1435 1436config SYS_P4080_ERRATUM_PCIE_A003 1437 bool 1438 1439config SYS_P4080_ERRATUM_SERDES8 1440 bool 1441 1442config SYS_P4080_ERRATUM_SERDES9 1443 bool 1444 1445config SYS_P4080_ERRATUM_SERDES_A001 1446 bool 1447 1448config SYS_P4080_ERRATUM_SERDES_A005 1449 bool 1450 1451config FSL_PCIE_DISABLE_ASPM 1452 bool 1453 1454config FSL_PCIE_RESET 1455 bool 1456 1457config SYS_FSL_QORIQ_CHASSIS1 1458 bool 1459 1460config SYS_FSL_QORIQ_CHASSIS2 1461 bool 1462 1463config SYS_FSL_NUM_LAWS 1464 int "Number of local access windows" 1465 depends on FSL_LAW 1466 default 32 if ARCH_B4420 || \ 1467 ARCH_B4860 || \ 1468 ARCH_P2041 || \ 1469 ARCH_P3041 || \ 1470 ARCH_P4080 || \ 1471 ARCH_P5020 || \ 1472 ARCH_P5040 || \ 1473 ARCH_T2080 || \ 1474 ARCH_T2081 || \ 1475 ARCH_T4160 || \ 1476 ARCH_T4240 1477 default 16 if ARCH_T1023 || \ 1478 ARCH_T1024 || \ 1479 ARCH_T1040 || \ 1480 ARCH_T1042 1481 default 12 if ARCH_BSC9131 || \ 1482 ARCH_BSC9132 || \ 1483 ARCH_C29X || \ 1484 ARCH_MPC8536 || \ 1485 ARCH_MPC8572 || \ 1486 ARCH_P1010 || \ 1487 ARCH_P1011 || \ 1488 ARCH_P1020 || \ 1489 ARCH_P1021 || \ 1490 ARCH_P1022 || \ 1491 ARCH_P1023 || \ 1492 ARCH_P1024 || \ 1493 ARCH_P1025 || \ 1494 ARCH_P2020 1495 default 10 if ARCH_MPC8544 || \ 1496 ARCH_MPC8548 || \ 1497 ARCH_MPC8568 || \ 1498 ARCH_MPC8569 1499 default 8 if ARCH_MPC8540 || \ 1500 ARCH_MPC8541 || \ 1501 ARCH_MPC8555 || \ 1502 ARCH_MPC8560 1503 help 1504 Number of local access windows. This is fixed per SoC. 1505 If not sure, do not change. 1506 1507config SYS_FSL_THREADS_PER_CORE 1508 int 1509 default 2 if E6500 1510 default 1 1511 1512config SYS_NUM_TLBCAMS 1513 int "Number of TLB CAM entries" 1514 default 64 if E500MC 1515 default 16 1516 help 1517 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1518 16 for other E500 SoCs. 1519 1520config SYS_PPC64 1521 bool 1522 1523config SYS_PPC_E500_USE_DEBUG_TLB 1524 bool 1525 1526config FSL_IFC 1527 bool 1528 1529config FSL_ELBC 1530 bool 1531 1532config SYS_PPC_E500_DEBUG_TLB 1533 int "Temporary TLB entry for external debugger" 1534 depends on SYS_PPC_E500_USE_DEBUG_TLB 1535 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1536 default 1 if ARCH_MPC8536 1537 default 2 if ARCH_MPC8572 || \ 1538 ARCH_P1011 || \ 1539 ARCH_P1020 || \ 1540 ARCH_P1021 || \ 1541 ARCH_P1022 || \ 1542 ARCH_P1024 || \ 1543 ARCH_P1025 || \ 1544 ARCH_P2020 1545 default 3 if ARCH_P1010 || \ 1546 ARCH_BSC9132 || \ 1547 ARCH_C29X 1548 help 1549 Select a temporary TLB entry to be used during boot to work 1550 around limitations in e500v1 and e500v2 external debugger 1551 support. This reduces the portions of the boot code where 1552 breakpoints and single stepping do not work. The value of this 1553 symbol should be set to the TLB1 entry to be used for this 1554 purpose. If unsure, do not change. 1555 1556config SYS_FSL_IFC_CLK_DIV 1557 int "Divider of platform clock" 1558 depends on FSL_IFC 1559 default 2 if ARCH_B4420 || \ 1560 ARCH_B4860 || \ 1561 ARCH_T1024 || \ 1562 ARCH_T1023 || \ 1563 ARCH_T1040 || \ 1564 ARCH_T1042 || \ 1565 ARCH_T4160 || \ 1566 ARCH_T4240 1567 default 1 1568 help 1569 Defines divider of platform clock(clock input to 1570 IFC controller). 1571 1572config SYS_FSL_LBC_CLK_DIV 1573 int "Divider of platform clock" 1574 depends on FSL_ELBC || ARCH_MPC8540 || \ 1575 ARCH_MPC8548 || ARCH_MPC8541 || \ 1576 ARCH_MPC8555 || ARCH_MPC8560 || \ 1577 ARCH_MPC8568 1578 1579 default 2 if ARCH_P2041 || \ 1580 ARCH_P3041 || \ 1581 ARCH_P4080 || \ 1582 ARCH_P5020 || \ 1583 ARCH_P5040 1584 default 1 1585 1586 help 1587 Defines divider of platform clock(clock input to 1588 eLBC controller). 1589 1590source "board/freescale/b4860qds/Kconfig" 1591source "board/freescale/bsc9131rdb/Kconfig" 1592source "board/freescale/bsc9132qds/Kconfig" 1593source "board/freescale/c29xpcie/Kconfig" 1594source "board/freescale/corenet_ds/Kconfig" 1595source "board/freescale/mpc8536ds/Kconfig" 1596source "board/freescale/mpc8541cds/Kconfig" 1597source "board/freescale/mpc8544ds/Kconfig" 1598source "board/freescale/mpc8548cds/Kconfig" 1599source "board/freescale/mpc8555cds/Kconfig" 1600source "board/freescale/mpc8568mds/Kconfig" 1601source "board/freescale/mpc8569mds/Kconfig" 1602source "board/freescale/mpc8572ds/Kconfig" 1603source "board/freescale/p1010rdb/Kconfig" 1604source "board/freescale/p1022ds/Kconfig" 1605source "board/freescale/p1023rdb/Kconfig" 1606source "board/freescale/p1_p2_rdb_pc/Kconfig" 1607source "board/freescale/p1_twr/Kconfig" 1608source "board/freescale/p2041rdb/Kconfig" 1609source "board/freescale/qemu-ppce500/Kconfig" 1610source "board/freescale/t102xqds/Kconfig" 1611source "board/freescale/t102xrdb/Kconfig" 1612source "board/freescale/t1040qds/Kconfig" 1613source "board/freescale/t104xrdb/Kconfig" 1614source "board/freescale/t208xqds/Kconfig" 1615source "board/freescale/t208xrdb/Kconfig" 1616source "board/freescale/t4qds/Kconfig" 1617source "board/freescale/t4rdb/Kconfig" 1618source "board/gdsys/p1022/Kconfig" 1619source "board/keymile/Kconfig" 1620source "board/sbc8548/Kconfig" 1621source "board/socrates/Kconfig" 1622source "board/varisys/cyrus/Kconfig" 1623source "board/xes/xpedite520x/Kconfig" 1624source "board/xes/xpedite537x/Kconfig" 1625source "board/xes/xpedite550x/Kconfig" 1626source "board/Arcturus/ucp1020/Kconfig" 1627 1628endmenu 1629