1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * (C) Copyright 2016
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 *
8 * Based on:
9 * Board functions for TI AM335X based boards
10 *
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 */
13
14 #include <common.h>
15 #include <env.h>
16 #include <errno.h>
17 #include <init.h>
18 #include <irq_func.h>
19 #include <spl.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/mem.h>
29 #include <asm/io.h>
30 #include <asm/emif.h>
31 #include <asm/gpio.h>
32 #include <i2c.h>
33 #include <miiphy.h>
34 #include <cpsw.h>
35 #include <power/tps65217.h>
36 #include <env_internal.h>
37 #include <watchdog.h>
38 #include "mmc.h"
39 #include "board.h"
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 static struct shc_eeprom __attribute__((section(".data"))) header;
44 static int shc_eeprom_valid;
45
46 /*
47 * Read header information from EEPROM into global structure.
48 */
read_eeprom(void)49 static int read_eeprom(void)
50 {
51 /* Check if baseboard eeprom is available */
52 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
53 puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
54 return -ENODEV;
55 }
56
57 /* read the eeprom using i2c */
58 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
59 sizeof(header))) {
60 puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
61 return -EIO;
62 }
63
64 if (header.magic != HDR_MAGIC) {
65 printf("Incorrect magic number (0x%x) in EEPROM\n",
66 header.magic);
67 return -EIO;
68 }
69
70 shc_eeprom_valid = 1;
71
72 return 0;
73 }
74
shc_request_gpio(void)75 static void shc_request_gpio(void)
76 {
77 gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
78 gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
79 gpio_request(RESET_GPIO, "reset");
80 gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
81 gpio_request(WIFI_RST_GPIO, "WIFI rst");
82 gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
83 gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
84 gpio_request(ENOC_RST_GPIO, "ENOC rst");
85 #if defined CONFIG_B_SAMPLE
86 gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
87 gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
88 gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
89 gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
90 #else
91 gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
92 gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
93 gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
94 gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
95 gpio_request(LED_PWM_GPIO, "LED PWM");
96 gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
97 #endif
98 gpio_request(BACK_BUTTON_GPIO, "Back button");
99 gpio_request(FRONT_BUTTON_GPIO, "Front button");
100 }
101
102 /*
103 * Function which forces all installed modules into running state for ICT
104 * testing. Called by SPL.
105 */
force_modules_running(void)106 static void __maybe_unused force_modules_running(void)
107 {
108 /* Wi-Fi power regulator enable - high = enabled */
109 gpio_direction_output(WIFI_REGEN_GPIO, 1);
110 /*
111 * Wait for Wi-Fi power regulator to reach a stable voltage
112 * (soft-start time, max. 350 µs)
113 */
114 __udelay(350);
115
116 /* Wi-Fi module reset - high = running */
117 gpio_direction_output(WIFI_RST_GPIO, 1);
118
119 /* ZigBee reset - high = running */
120 gpio_direction_output(ZIGBEE_RST_GPIO, 1);
121
122 /* BidCos reset - high = running */
123 gpio_direction_output(BIDCOS_RST_GPIO, 1);
124
125 #if !defined(CONFIG_B_SAMPLE)
126 /* Z-Wave reset - high = running */
127 gpio_direction_output(Z_WAVE_RST_GPIO, 1);
128 #endif
129
130 /* EnOcean reset - low = running */
131 gpio_direction_output(ENOC_RST_GPIO, 0);
132 }
133
134 /*
135 * Function which forces all installed modules into reset - to be released by
136 * the OS, called by SPL
137 */
force_modules_reset(void)138 static void __maybe_unused force_modules_reset(void)
139 {
140 /* Wi-Fi module reset - low = reset */
141 gpio_direction_output(WIFI_RST_GPIO, 0);
142
143 /* Wi-Fi power regulator enable - low = disabled */
144 gpio_direction_output(WIFI_REGEN_GPIO, 0);
145
146 /* ZigBee reset - low = reset */
147 gpio_direction_output(ZIGBEE_RST_GPIO, 0);
148
149 /* BidCos reset - low = reset */
150 /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
151
152 #if !defined(CONFIG_B_SAMPLE)
153 /* Z-Wave reset - low = reset */
154 gpio_direction_output(Z_WAVE_RST_GPIO, 0);
155 #endif
156
157 /* EnOcean reset - high = reset*/
158 gpio_direction_output(ENOC_RST_GPIO, 1);
159 }
160
161 /*
162 * Function to set the LEDs in the state "Bootloader booting"
163 */
leds_set_booting(void)164 static void __maybe_unused leds_set_booting(void)
165 {
166 #if defined(CONFIG_B_SAMPLE)
167
168 /* Turn all red LEDs on */
169 gpio_direction_output(LED_PWR_RD_GPIO, 1);
170 gpio_direction_output(LED_CONN_RD_GPIO, 1);
171
172 #else /* All other SHCs starting with B2-Sample */
173 /* Set the PWM GPIO */
174 gpio_direction_output(LED_PWM_GPIO, 1);
175 /* Turn all red LEDs on */
176 gpio_direction_output(LED_PWR_RD_GPIO, 1);
177 gpio_direction_output(LED_LAN_RD_GPIO, 1);
178 gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
179
180 #endif
181 }
182
183 /*
184 * Function to set the LEDs in the state "Bootloader error"
185 */
leds_set_failure(int state)186 static void leds_set_failure(int state)
187 {
188 #if defined(CONFIG_B_SAMPLE)
189 /* Turn all blue and green LEDs off */
190 gpio_set_value(LED_PWR_BL_GPIO, 0);
191 gpio_set_value(LED_PWR_GN_GPIO, 0);
192 gpio_set_value(LED_CONN_BL_GPIO, 0);
193 gpio_set_value(LED_CONN_GN_GPIO, 0);
194
195 /* Turn all red LEDs to 'state' */
196 gpio_set_value(LED_PWR_RD_GPIO, state);
197 gpio_set_value(LED_CONN_RD_GPIO, state);
198
199 #else /* All other SHCs starting with B2-Sample */
200 /* Set the PWM GPIO */
201 gpio_direction_output(LED_PWM_GPIO, 1);
202
203 /* Turn all blue LEDs off */
204 gpio_set_value(LED_PWR_BL_GPIO, 0);
205 gpio_set_value(LED_LAN_BL_GPIO, 0);
206 gpio_set_value(LED_CLOUD_BL_GPIO, 0);
207
208 /* Turn all red LEDs to 'state' */
209 gpio_set_value(LED_PWR_RD_GPIO, state);
210 gpio_set_value(LED_LAN_RD_GPIO, state);
211 gpio_set_value(LED_CLOUD_RD_GPIO, state);
212 #endif
213 }
214
215 /*
216 * Function to set the LEDs in the state "Bootloader finished"
217 */
leds_set_finish(void)218 static void leds_set_finish(void)
219 {
220 #if defined(CONFIG_B_SAMPLE)
221 /* Turn all LEDs off */
222 gpio_set_value(LED_PWR_BL_GPIO, 0);
223 gpio_set_value(LED_PWR_RD_GPIO, 0);
224 gpio_set_value(LED_PWR_GN_GPIO, 0);
225 gpio_set_value(LED_CONN_BL_GPIO, 0);
226 gpio_set_value(LED_CONN_RD_GPIO, 0);
227 gpio_set_value(LED_CONN_GN_GPIO, 0);
228 #else /* All other SHCs starting with B2-Sample */
229 /* Turn all LEDs off */
230 gpio_set_value(LED_PWR_BL_GPIO, 0);
231 gpio_set_value(LED_PWR_RD_GPIO, 0);
232 gpio_set_value(LED_LAN_BL_GPIO, 0);
233 gpio_set_value(LED_LAN_RD_GPIO, 0);
234 gpio_set_value(LED_CLOUD_BL_GPIO, 0);
235 gpio_set_value(LED_CLOUD_RD_GPIO, 0);
236
237 /* Turn off the PWM GPIO and mux it to EHRPWM */
238 gpio_set_value(LED_PWM_GPIO, 0);
239 enable_shc_board_pwm_pin_mux();
240 #endif
241 }
242
check_button_status(void)243 static void check_button_status(void)
244 {
245 ulong value;
246 gpio_direction_input(FRONT_BUTTON_GPIO);
247 value = gpio_get_value(FRONT_BUTTON_GPIO);
248
249 if (value == 0) {
250 printf("front button activated !\n");
251 env_set("harakiri", "1");
252 }
253 }
254
255 #if defined(CONFIG_SPL_BUILD)
256 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)257 int spl_start_uboot(void)
258 {
259 return 1;
260 }
261 #endif
262
shc_board_early_init(void)263 static void shc_board_early_init(void)
264 {
265 shc_request_gpio();
266 # ifdef CONFIG_SHC_ICT
267 /* Force all modules into enabled state for ICT testing */
268 force_modules_running();
269 # else
270 /* Force all modules to enter Reset state until released by the OS */
271 force_modules_reset();
272 # endif
273 leds_set_booting();
274 }
275
276 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
277
278 #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
279 #define OSC (V_OSCK/1000000)
280 /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
281 #define MPUPLL_N (4-1)
282 /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
283 #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
284
285 const struct dpll_params dpll_ddr_shc = {
286 400, OSC-1, 1, -1, -1, -1, -1};
287
get_dpll_ddr_params(void)288 const struct dpll_params *get_dpll_ddr_params(void)
289 {
290 return &dpll_ddr_shc;
291 }
292
293 /*
294 * As we enabled downspread SSC with 1.8%, the values needed to be corrected
295 * such that the 20% overshoot will not lead to too high frequencies.
296 * In all cases, this is achieved by subtracting one from M (6 MHz less).
297 * Example: 600 MHz CPU
298 * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
299 * 600 MHz - 6 MHz (1x Fref) = 594 MHz
300 * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
301 * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
302 * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
303 */
304 const struct dpll_params dpll_mpu_shc_opp100 = {
305 99, MPUPLL_N, 1, -1, -1, -1, -1};
306
am33xx_spl_board_init(void)307 void am33xx_spl_board_init(void)
308 {
309 int sil_rev;
310 int mpu_vdd;
311
312 puts(BOARD_ID_STR);
313
314 /*
315 * Set CORE Frequency to OPP100
316 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
317 */
318 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
319
320 sil_rev = readl(&cdev->deviceid) >> 28;
321 if (sil_rev < 2) {
322 puts("We do not support Silicon Revisions below 2.0!\n");
323 return;
324 }
325
326 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
327 if (i2c_probe(TPS65217_CHIP_PM))
328 return;
329
330 /*
331 * Retrieve the CPU max frequency by reading the efuse
332 * SHC-Default: 600 MHz
333 */
334 switch (dpll_mpu_opp100.m) {
335 case MPUPLL_M_1000:
336 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
337 break;
338 case MPUPLL_M_800:
339 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
340 break;
341 case MPUPLL_M_720:
342 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
343 break;
344 case MPUPLL_M_600:
345 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
346 break;
347 case MPUPLL_M_300:
348 mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
349 break;
350 default:
351 puts("Cannot determine the frequency, failing!\n");
352 return;
353 }
354
355 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
356 puts("tps65217_voltage_update failure\n");
357 return;
358 }
359
360 /* Set MPU Frequency to what we detected */
361 printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
362 printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
363 dpll_mpu_shc_opp100.m);
364 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
365
366 /* Enable Spread Spectrum for this freq to be clean on EMI side */
367 set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
368
369 /*
370 * Using the default voltages for the PMIC (TPS65217D)
371 * LS1 = 1.8V (VDD_1V8)
372 * LS2 = 3.3V (VDD_3V3A)
373 * LDO1 = 1.8V (VIO and VRTC)
374 * LDO2 = 3.3V (VDD_3V3AUX)
375 */
376 shc_board_early_init();
377 }
378
set_uart_mux_conf(void)379 void set_uart_mux_conf(void)
380 {
381 enable_uart0_pin_mux();
382 }
383
set_mux_conf_regs(void)384 void set_mux_conf_regs(void)
385 {
386 enable_shc_board_pin_mux();
387 }
388
389 const struct ctrl_ioregs ioregs_evmsk = {
390 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
391 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
392 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
393 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
394 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
395 };
396
397 static const struct ddr_data ddr3_shc_data = {
398 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
399 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
400 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
401 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
402 };
403
404 static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
405 .cmd0csratio = MT41K256M16HA125E_RATIO,
406 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
407
408 .cmd1csratio = MT41K256M16HA125E_RATIO,
409 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
410
411 .cmd2csratio = MT41K256M16HA125E_RATIO,
412 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
413 };
414
415 static struct emif_regs ddr3_shc_emif_reg_data = {
416 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
417 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
418 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
419 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
420 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
421 .zq_config = MT41K256M16HA125E_ZQ_CFG,
422 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
423 PHY_EN_DYN_PWRDN,
424 };
425
sdram_init(void)426 void sdram_init(void)
427 {
428 /* Configure the DDR3 RAM */
429 config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
430 &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
431 }
432 #endif
433
434 /*
435 * Basic board specific setup. Pinmux has been handled already.
436 */
board_init(void)437 int board_init(void)
438 {
439 #if defined(CONFIG_HW_WATCHDOG)
440 hw_watchdog_init();
441 #endif
442 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
443 if (read_eeprom() < 0)
444 puts("EEPROM Content Invalid.\n");
445
446 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
447 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
448 gpmc_init();
449 #endif
450 shc_request_gpio();
451
452 return 0;
453 }
454
455 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)456 int board_late_init(void)
457 {
458 check_button_status();
459 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
460 if (shc_eeprom_valid)
461 if (is_valid_ethaddr(header.mac_addr))
462 eth_env_set_enetaddr("ethaddr", header.mac_addr);
463 #endif
464
465 return 0;
466 }
467 #endif
468
469 #if defined(CONFIG_USB_ETHER) && \
470 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
board_eth_init(bd_t * bis)471 int board_eth_init(bd_t *bis)
472 {
473 return usb_eth_initialize(bis);
474 }
475 #endif
476
477 #ifdef CONFIG_SHOW_BOOT_PROGRESS
bosch_check_reset_pin(void)478 static void bosch_check_reset_pin(void)
479 {
480 if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
481 printf("Resetting ...\n");
482 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
483 disable_interrupts();
484 reset_cpu(0);
485 /*NOTREACHED*/
486 }
487 }
488
hang_bosch(const char * cause,int code)489 static void hang_bosch(const char *cause, int code)
490 {
491 int lv;
492
493 gpio_direction_input(RESET_GPIO);
494
495 /* Enable reset pin interrupt on falling edge */
496 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
497 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
498 enable_interrupts();
499
500 puts(cause);
501 for (;;) {
502 for (lv = 0; lv < code; lv++) {
503 bosch_check_reset_pin();
504 leds_set_failure(1);
505 __udelay(150 * 1000);
506 leds_set_failure(0);
507 __udelay(150 * 1000);
508 }
509 #if defined(BLINK_CODE)
510 __udelay(300 * 1000);
511 #endif
512 }
513 }
514
show_boot_progress(int val)515 void show_boot_progress(int val)
516 {
517 switch (val) {
518 case BOOTSTAGE_ID_NEED_RESET:
519 hang_bosch("need reset", 4);
520 break;
521 }
522 }
523
arch_preboot_os(void)524 void arch_preboot_os(void)
525 {
526 leds_set_finish();
527 }
528 #endif
529