1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <miiphy.h>
8 #include <netdev.h>
9
10 #include <asm/arch/clock.h>
11 #include <asm/io.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
dram_init(void)15 int dram_init(void)
16 {
17 gd->ram_size = PHYS_SDRAM_SIZE;
18
19 return 0;
20 }
21
22 #if IS_ENABLED(CONFIG_FEC_MXC)
setup_fec(void)23 static int setup_fec(void)
24 {
25 struct iomuxc_gpr_base_regs *gpr =
26 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
27
28 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
29 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
30
31 return 0;
32 }
33
board_phy_config(struct phy_device * phydev)34 int board_phy_config(struct phy_device *phydev)
35 {
36 /* enable rgmii rxc skew and phy mode select to RGMII copper */
37 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
38 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
39
40 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
41 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
42 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
43 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
44
45 if (phydev->drv->config)
46 phydev->drv->config(phydev);
47 return 0;
48 }
49 #endif
50
board_init(void)51 int board_init(void)
52 {
53 if (IS_ENABLED(CONFIG_FEC_MXC))
54 setup_fec();
55
56 return 0;
57 }
58
board_mmc_get_env_dev(int devno)59 int board_mmc_get_env_dev(int devno)
60 {
61 return devno;
62 }
63
board_late_init(void)64 int board_late_init(void)
65 {
66 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
67 env_set("board_name", "EVK");
68 env_set("board_rev", "iMX8MM");
69 #endif
70 return 0;
71 }
72