1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * bcm2835 sdhost driver.
4 *
5 * The 2835 has two SD controllers: The Arasan sdhci controller
6 * (supported by the iproc driver) and a custom sdhost controller
7 * (supported by this driver).
8 *
9 * The sdhci controller supports both sdcard and sdio. The sdhost
10 * controller supports the sdcard only, but has better performance.
11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
12 * the sdhost controller allows to use the sdhci controller for wifi
13 * support.
14 *
15 * The configuration is done by devicetree via pin muxing. Both
16 * SD controller are available on the same pins (2 pin groups = pin 22
17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
18 * at the same time with different pin groups.
19 *
20 * This code was ported to U-Boot by
21 * Alexander Graf <agraf@suse.de>
22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
23 * Phil Elwell <phil@raspberrypi.org>
24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
25 * which is based on
26 * mmc-bcm2835.c by Gellert Weisz
27 * which is, in turn, based on
28 * sdhci-bcm2708.c by Broadcom
29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
30 * sdhci.c and sdhci-pci.c by Pierre Ossman
31 */
32 #include <clk.h>
33 #include <common.h>
34 #include <dm.h>
35 #include <mmc.h>
36 #include <asm/arch/msg.h>
37 #include <asm/arch/mbox.h>
38 #include <asm/unaligned.h>
39 #include <linux/compat.h>
40 #include <linux/io.h>
41 #include <linux/iopoll.h>
42 #include <linux/sizes.h>
43 #include <mach/gpio.h>
44 #include <power/regulator.h>
45
46 #define msleep(a) udelay(a * 1000)
47
48 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
49 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
50 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
51 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
52 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
53 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
54 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
55 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
56 #define SDHSTS 0x20 /* SD host status - 11 R/W */
57 #define SDVDD 0x30 /* SD card power control - 1 R/W */
58 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
59 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
60 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
61 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
62 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
63
64 #define SDCMD_NEW_FLAG 0x8000
65 #define SDCMD_FAIL_FLAG 0x4000
66 #define SDCMD_BUSYWAIT 0x800
67 #define SDCMD_NO_RESPONSE 0x400
68 #define SDCMD_LONG_RESPONSE 0x200
69 #define SDCMD_WRITE_CMD 0x80
70 #define SDCMD_READ_CMD 0x40
71 #define SDCMD_CMD_MASK 0x3f
72
73 #define SDCDIV_MAX_CDIV 0x7ff
74
75 #define SDHSTS_BUSY_IRPT 0x400
76 #define SDHSTS_BLOCK_IRPT 0x200
77 #define SDHSTS_SDIO_IRPT 0x100
78 #define SDHSTS_REW_TIME_OUT 0x80
79 #define SDHSTS_CMD_TIME_OUT 0x40
80 #define SDHSTS_CRC16_ERROR 0x20
81 #define SDHSTS_CRC7_ERROR 0x10
82 #define SDHSTS_FIFO_ERROR 0x08
83 #define SDHSTS_DATA_FLAG 0x01
84
85 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
86 SDHSTS_BLOCK_IRPT | \
87 SDHSTS_SDIO_IRPT | \
88 SDHSTS_REW_TIME_OUT | \
89 SDHSTS_CMD_TIME_OUT | \
90 SDHSTS_CRC16_ERROR | \
91 SDHSTS_CRC7_ERROR | \
92 SDHSTS_FIFO_ERROR)
93
94 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
95 SDHSTS_CRC16_ERROR | \
96 SDHSTS_REW_TIME_OUT | \
97 SDHSTS_FIFO_ERROR)
98
99 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
100 SDHSTS_TRANSFER_ERROR_MASK)
101
102 #define SDHCFG_BUSY_IRPT_EN BIT(10)
103 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
104 #define SDHCFG_SDIO_IRPT_EN BIT(5)
105 #define SDHCFG_DATA_IRPT_EN BIT(4)
106 #define SDHCFG_SLOW_CARD BIT(3)
107 #define SDHCFG_WIDE_EXT_BUS BIT(2)
108 #define SDHCFG_WIDE_INT_BUS BIT(1)
109 #define SDHCFG_REL_CMD_LINE BIT(0)
110
111 #define SDVDD_POWER_OFF 0
112 #define SDVDD_POWER_ON 1
113
114 #define SDEDM_FORCE_DATA_MODE BIT(19)
115 #define SDEDM_CLOCK_PULSE BIT(20)
116 #define SDEDM_BYPASS BIT(21)
117
118 #define SDEDM_FIFO_FILL_SHIFT 4
119 #define SDEDM_FIFO_FILL_MASK 0x1f
edm_fifo_fill(u32 edm)120 static u32 edm_fifo_fill(u32 edm)
121 {
122 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
123 }
124
125 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
126 #define SDEDM_READ_THRESHOLD_SHIFT 14
127 #define SDEDM_THRESHOLD_MASK 0x1f
128
129 #define SDEDM_FSM_MASK 0xf
130 #define SDEDM_FSM_IDENTMODE 0x0
131 #define SDEDM_FSM_DATAMODE 0x1
132 #define SDEDM_FSM_READDATA 0x2
133 #define SDEDM_FSM_WRITEDATA 0x3
134 #define SDEDM_FSM_READWAIT 0x4
135 #define SDEDM_FSM_READCRC 0x5
136 #define SDEDM_FSM_WRITECRC 0x6
137 #define SDEDM_FSM_WRITEWAIT1 0x7
138 #define SDEDM_FSM_POWERDOWN 0x8
139 #define SDEDM_FSM_POWERUP 0x9
140 #define SDEDM_FSM_WRITESTART1 0xa
141 #define SDEDM_FSM_WRITESTART2 0xb
142 #define SDEDM_FSM_GENPULSES 0xc
143 #define SDEDM_FSM_WRITEWAIT2 0xd
144 #define SDEDM_FSM_STARTPOWDOWN 0xf
145
146 #define SDDATA_FIFO_WORDS 16
147
148 #define FIFO_READ_THRESHOLD 4
149 #define FIFO_WRITE_THRESHOLD 4
150 #define SDDATA_FIFO_PIO_BURST 8
151
152 #define SDHST_TIMEOUT_MAX_USEC 100000
153
154 struct bcm2835_plat {
155 struct mmc_config cfg;
156 struct mmc mmc;
157 };
158
159 struct bcm2835_host {
160 void __iomem *ioaddr;
161 u32 phys_addr;
162
163 int clock; /* Current clock speed */
164 unsigned int max_clk; /* Max possible freq */
165 unsigned int blocks; /* remaining PIO blocks */
166
167 u32 ns_per_fifo_word;
168
169 /* cached registers */
170 u32 hcfg;
171 u32 cdiv;
172
173 struct mmc_cmd *cmd; /* Current command */
174 struct mmc_data *data; /* Current data request */
175 bool use_busy:1; /* Wait for busy interrupt */
176
177 struct udevice *dev;
178 struct mmc *mmc;
179 struct bcm2835_plat *plat;
180 };
181
bcm2835_dumpregs(struct bcm2835_host * host)182 static void bcm2835_dumpregs(struct bcm2835_host *host)
183 {
184 dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
185 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
186 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
187 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
188 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
189 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
190 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
191 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
192 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
193 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
194 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
195 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
196 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
197 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
198 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
199 dev_dbg(dev, "===========================================\n");
200 }
201
bcm2835_reset_internal(struct bcm2835_host * host)202 static void bcm2835_reset_internal(struct bcm2835_host *host)
203 {
204 u32 temp;
205
206 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
207 writel(0, host->ioaddr + SDCMD);
208 writel(0, host->ioaddr + SDARG);
209 /* Set timeout to a big enough value so we don't hit it */
210 writel(0xf00000, host->ioaddr + SDTOUT);
211 writel(0, host->ioaddr + SDCDIV);
212 /* Clear status register */
213 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
214 writel(0, host->ioaddr + SDHCFG);
215 writel(0, host->ioaddr + SDHBCT);
216 writel(0, host->ioaddr + SDHBLC);
217
218 /* Limit fifo usage due to silicon bug */
219 temp = readl(host->ioaddr + SDEDM);
220 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
221 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
222 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
223 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
224 writel(temp, host->ioaddr + SDEDM);
225 /* Wait for FIFO threshold to populate */
226 msleep(20);
227 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
228 /* Wait for all components to go through power on cycle */
229 msleep(20);
230 host->clock = 0;
231 writel(host->hcfg, host->ioaddr + SDHCFG);
232 writel(host->cdiv, host->ioaddr + SDCDIV);
233 }
234
bcm2835_wait_transfer_complete(struct bcm2835_host * host)235 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
236 {
237 ulong tstart_ms = get_timer(0);
238
239 while (1) {
240 u32 edm, fsm;
241
242 edm = readl(host->ioaddr + SDEDM);
243 fsm = edm & SDEDM_FSM_MASK;
244
245 if ((fsm == SDEDM_FSM_IDENTMODE) ||
246 (fsm == SDEDM_FSM_DATAMODE))
247 break;
248
249 if ((fsm == SDEDM_FSM_READWAIT) ||
250 (fsm == SDEDM_FSM_WRITESTART1) ||
251 (fsm == SDEDM_FSM_READDATA)) {
252 writel(edm | SDEDM_FORCE_DATA_MODE,
253 host->ioaddr + SDEDM);
254 break;
255 }
256
257 /* Error out after ~1s */
258 ulong tlapse_ms = get_timer(tstart_ms);
259 if ( tlapse_ms > 1000 /* ms */ ) {
260
261 dev_err(host->dev,
262 "wait_transfer_complete - still waiting after %lu ms\n",
263 tlapse_ms);
264 bcm2835_dumpregs(host);
265 return -ETIMEDOUT;
266 }
267 }
268
269 return 0;
270 }
271
bcm2835_transfer_block_pio(struct bcm2835_host * host,bool is_read)272 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
273 {
274 struct mmc_data *data = host->data;
275 size_t blksize = data->blocksize;
276 int copy_words;
277 u32 hsts = 0;
278 u32 *buf;
279
280 if (blksize % sizeof(u32))
281 return -EINVAL;
282
283 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
284
285 if (is_read)
286 data->dest += blksize;
287 else
288 data->src += blksize;
289
290 copy_words = blksize / sizeof(u32);
291
292 /*
293 * Copy all contents from/to the FIFO as far as it reaches,
294 * then wait for it to fill/empty again and rewind.
295 */
296 while (copy_words) {
297 int burst_words, words;
298 u32 edm;
299
300 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
301 edm = readl(host->ioaddr + SDEDM);
302 if (is_read)
303 words = edm_fifo_fill(edm);
304 else
305 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
306
307 if (words < burst_words) {
308 int fsm_state = (edm & SDEDM_FSM_MASK);
309
310 if ((is_read &&
311 (fsm_state != SDEDM_FSM_READDATA &&
312 fsm_state != SDEDM_FSM_READWAIT &&
313 fsm_state != SDEDM_FSM_READCRC)) ||
314 (!is_read &&
315 (fsm_state != SDEDM_FSM_WRITEDATA &&
316 fsm_state != SDEDM_FSM_WRITEWAIT1 &&
317 fsm_state != SDEDM_FSM_WRITEWAIT2 &&
318 fsm_state != SDEDM_FSM_WRITECRC &&
319 fsm_state != SDEDM_FSM_WRITESTART1 &&
320 fsm_state != SDEDM_FSM_WRITESTART2))) {
321 hsts = readl(host->ioaddr + SDHSTS);
322 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
323 if (hsts & SDHSTS_ERROR_MASK)
324 break;
325 }
326
327 continue;
328 } else if (words > copy_words) {
329 words = copy_words;
330 }
331
332 copy_words -= words;
333
334 /* Copy current chunk to/from the FIFO */
335 while (words) {
336 if (is_read)
337 *(buf++) = readl(host->ioaddr + SDDATA);
338 else
339 writel(*(buf++), host->ioaddr + SDDATA);
340 words--;
341 }
342 }
343
344 return 0;
345 }
346
bcm2835_transfer_pio(struct bcm2835_host * host)347 static int bcm2835_transfer_pio(struct bcm2835_host *host)
348 {
349 u32 sdhsts;
350 bool is_read;
351 int ret = 0;
352
353 is_read = (host->data->flags & MMC_DATA_READ) != 0;
354 ret = bcm2835_transfer_block_pio(host, is_read);
355 if (ret)
356 return ret;
357
358 sdhsts = readl(host->ioaddr + SDHSTS);
359 if (sdhsts & (SDHSTS_CRC16_ERROR |
360 SDHSTS_CRC7_ERROR |
361 SDHSTS_FIFO_ERROR)) {
362 printf("%s transfer error - HSTS %08x\n",
363 is_read ? "read" : "write", sdhsts);
364 ret = -EILSEQ;
365 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
366 SDHSTS_REW_TIME_OUT))) {
367 printf("%s timeout error - HSTS %08x\n",
368 is_read ? "read" : "write", sdhsts);
369 ret = -ETIMEDOUT;
370 }
371
372 return ret;
373 }
374
bcm2835_prepare_data(struct bcm2835_host * host,struct mmc_cmd * cmd,struct mmc_data * data)375 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
376 struct mmc_data *data)
377 {
378 WARN_ON(host->data);
379
380 host->data = data;
381 if (!data)
382 return;
383
384 /* Use PIO */
385 host->blocks = data->blocks;
386
387 writel(data->blocksize, host->ioaddr + SDHBCT);
388 writel(data->blocks, host->ioaddr + SDHBLC);
389 }
390
bcm2835_read_wait_sdcmd(struct bcm2835_host * host)391 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
392 {
393 u32 value;
394 int ret;
395 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
396
397 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
398 !(value & SDCMD_NEW_FLAG), timeout_us);
399 if (ret == -ETIMEDOUT)
400 printf("%s: timeout (%d us)\n", __func__, timeout_us);
401
402 return value;
403 }
404
bcm2835_send_command(struct bcm2835_host * host,struct mmc_cmd * cmd,struct mmc_data * data)405 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
406 struct mmc_data *data)
407 {
408 u32 sdcmd, sdhsts;
409
410 WARN_ON(host->cmd);
411
412 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
413 printf("unsupported response type!\n");
414 return -EINVAL;
415 }
416
417 sdcmd = bcm2835_read_wait_sdcmd(host);
418 if (sdcmd & SDCMD_NEW_FLAG) {
419 printf("previous command never completed.\n");
420 bcm2835_dumpregs(host);
421 return -EBUSY;
422 }
423
424 host->cmd = cmd;
425
426 /* Clear any error flags */
427 sdhsts = readl(host->ioaddr + SDHSTS);
428 if (sdhsts & SDHSTS_ERROR_MASK)
429 writel(sdhsts, host->ioaddr + SDHSTS);
430
431 bcm2835_prepare_data(host, cmd, data);
432
433 writel(cmd->cmdarg, host->ioaddr + SDARG);
434
435 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
436
437 host->use_busy = false;
438 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
439 sdcmd |= SDCMD_NO_RESPONSE;
440 } else {
441 if (cmd->resp_type & MMC_RSP_136)
442 sdcmd |= SDCMD_LONG_RESPONSE;
443 if (cmd->resp_type & MMC_RSP_BUSY) {
444 sdcmd |= SDCMD_BUSYWAIT;
445 host->use_busy = true;
446 }
447 }
448
449 if (data) {
450 if (data->flags & MMC_DATA_WRITE)
451 sdcmd |= SDCMD_WRITE_CMD;
452 if (data->flags & MMC_DATA_READ)
453 sdcmd |= SDCMD_READ_CMD;
454 }
455
456 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
457
458 return 0;
459 }
460
bcm2835_finish_command(struct bcm2835_host * host)461 static int bcm2835_finish_command(struct bcm2835_host *host)
462 {
463 struct mmc_cmd *cmd = host->cmd;
464 u32 sdcmd;
465 int ret = 0;
466
467 sdcmd = bcm2835_read_wait_sdcmd(host);
468
469 /* Check for errors */
470 if (sdcmd & SDCMD_NEW_FLAG) {
471 printf("command never completed.\n");
472 bcm2835_dumpregs(host);
473 return -EIO;
474 } else if (sdcmd & SDCMD_FAIL_FLAG) {
475 u32 sdhsts = readl(host->ioaddr + SDHSTS);
476
477 /* Clear the errors */
478 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
479
480 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
481 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
482 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
483 ret = -ETIMEDOUT;
484 } else {
485 printf("unexpected command %d error\n",
486 host->cmd->cmdidx);
487 bcm2835_dumpregs(host);
488 ret = -EILSEQ;
489 }
490
491 return ret;
492 }
493 }
494
495 if (cmd->resp_type & MMC_RSP_PRESENT) {
496 if (cmd->resp_type & MMC_RSP_136) {
497 int i;
498
499 for (i = 0; i < 4; i++) {
500 cmd->response[3 - i] =
501 readl(host->ioaddr + SDRSP0 + i * 4);
502 }
503 } else {
504 cmd->response[0] = readl(host->ioaddr + SDRSP0);
505 }
506 }
507
508 /* Processed actual command. */
509 host->cmd = NULL;
510
511 return ret;
512 }
513
bcm2835_check_cmd_error(struct bcm2835_host * host,u32 intmask)514 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
515 {
516 int ret = -EINVAL;
517
518 if (!(intmask & SDHSTS_ERROR_MASK))
519 return 0;
520
521 if (!host->cmd)
522 return -EINVAL;
523
524 printf("sdhost_busy_irq: intmask %08x\n", intmask);
525 if (intmask & SDHSTS_CRC7_ERROR) {
526 ret = -EILSEQ;
527 } else if (intmask & (SDHSTS_CRC16_ERROR |
528 SDHSTS_FIFO_ERROR)) {
529 ret = -EILSEQ;
530 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
531 ret = -ETIMEDOUT;
532 }
533 bcm2835_dumpregs(host);
534 return ret;
535 }
536
bcm2835_check_data_error(struct bcm2835_host * host,u32 intmask)537 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
538 {
539 int ret = 0;
540
541 if (!host->data)
542 return 0;
543 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
544 ret = -EILSEQ;
545 if (intmask & SDHSTS_REW_TIME_OUT)
546 ret = -ETIMEDOUT;
547
548 if (ret)
549 printf("%s:%d %d\n", __func__, __LINE__, ret);
550
551 return ret;
552 }
553
bcm2835_transmit(struct bcm2835_host * host)554 static int bcm2835_transmit(struct bcm2835_host *host)
555 {
556 u32 intmask = readl(host->ioaddr + SDHSTS);
557 int ret;
558
559 /* Check for errors */
560 ret = bcm2835_check_data_error(host, intmask);
561 if (ret)
562 return ret;
563
564 ret = bcm2835_check_cmd_error(host, intmask);
565 if (ret)
566 return ret;
567
568 /* Handle wait for busy end */
569 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
570 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
571 host->use_busy = false;
572 bcm2835_finish_command(host);
573 }
574
575 /* Handle PIO data transfer */
576 if (host->data) {
577 ret = bcm2835_transfer_pio(host);
578 if (ret)
579 return ret;
580 host->blocks--;
581 if (host->blocks == 0) {
582 /* Wait for command to complete for real */
583 ret = bcm2835_wait_transfer_complete(host);
584 if (ret)
585 return ret;
586 /* Transfer complete */
587 host->data = NULL;
588 }
589 }
590
591 return 0;
592 }
593
bcm2835_set_clock(struct bcm2835_host * host,unsigned int clock)594 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
595 {
596 int div;
597
598 /* The SDCDIV register has 11 bits, and holds (div - 2). But
599 * in data mode the max is 50MHz wihout a minimum, and only
600 * the bottom 3 bits are used. Since the switch over is
601 * automatic (unless we have marked the card as slow...),
602 * chosen values have to make sense in both modes. Ident mode
603 * must be 100-400KHz, so can range check the requested
604 * clock. CMD15 must be used to return to data mode, so this
605 * can be monitored.
606 *
607 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
608 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
609 *
610 * 623->400KHz/27.8MHz
611 * reset value (507)->491159/50MHz
612 *
613 * BUT, the 3-bit clock divisor in data mode is too small if
614 * the core clock is higher than 250MHz, so instead use the
615 * SLOW_CARD configuration bit to force the use of the ident
616 * clock divisor at all times.
617 */
618
619 if (clock < 100000) {
620 /* Can't stop the clock, but make it as slow as possible
621 * to show willing
622 */
623 host->cdiv = SDCDIV_MAX_CDIV;
624 writel(host->cdiv, host->ioaddr + SDCDIV);
625 return;
626 }
627
628 div = host->max_clk / clock;
629 if (div < 2)
630 div = 2;
631 if ((host->max_clk / div) > clock)
632 div++;
633 div -= 2;
634
635 if (div > SDCDIV_MAX_CDIV)
636 div = SDCDIV_MAX_CDIV;
637
638 clock = host->max_clk / (div + 2);
639 host->mmc->clock = clock;
640
641 /* Calibrate some delays */
642
643 host->ns_per_fifo_word = (1000000000 / clock) *
644 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
645
646 host->cdiv = div;
647 writel(host->cdiv, host->ioaddr + SDCDIV);
648
649 /* Set the timeout to 500ms */
650 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
651 }
652
is_power_of_2(u64 x)653 static inline int is_power_of_2(u64 x)
654 {
655 return !(x & (x - 1));
656 }
657
bcm2835_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)658 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
659 struct mmc_data *data)
660 {
661 struct bcm2835_host *host = dev_get_priv(dev);
662 u32 edm, fsm;
663 int ret = 0;
664
665 if (data && !is_power_of_2(data->blocksize)) {
666 printf("unsupported block size (%d bytes)\n", data->blocksize);
667
668 if (cmd)
669 return -EINVAL;
670 }
671
672 edm = readl(host->ioaddr + SDEDM);
673 fsm = edm & SDEDM_FSM_MASK;
674
675 if ((fsm != SDEDM_FSM_IDENTMODE) &&
676 (fsm != SDEDM_FSM_DATAMODE) &&
677 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
678 printf("previous command (%d) not complete (EDM %08x)\n",
679 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
680 bcm2835_dumpregs(host);
681
682 if (cmd)
683 return -EILSEQ;
684
685 return 0;
686 }
687
688 if (cmd) {
689 ret = bcm2835_send_command(host, cmd, data);
690 if (!ret && !host->use_busy)
691 ret = bcm2835_finish_command(host);
692 }
693
694 /* Wait for completion of busy signal or data transfer */
695 while (host->use_busy || host->data) {
696 ret = bcm2835_transmit(host);
697 if (ret)
698 break;
699 }
700
701 return ret;
702 }
703
bcm2835_set_ios(struct udevice * dev)704 static int bcm2835_set_ios(struct udevice *dev)
705 {
706 struct bcm2835_host *host = dev_get_priv(dev);
707 struct mmc *mmc = mmc_get_mmc_dev(dev);
708
709 if (!mmc->clock || mmc->clock != host->clock) {
710 bcm2835_set_clock(host, mmc->clock);
711 host->clock = mmc->clock;
712 }
713
714 /* set bus width */
715 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
716 if (mmc->bus_width == 4)
717 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
718
719 host->hcfg |= SDHCFG_WIDE_INT_BUS;
720
721 /* Disable clever clock switching, to cope with fast core clocks */
722 host->hcfg |= SDHCFG_SLOW_CARD;
723
724 writel(host->hcfg, host->ioaddr + SDHCFG);
725
726 return 0;
727 }
728
bcm2835_add_host(struct bcm2835_host * host)729 static void bcm2835_add_host(struct bcm2835_host *host)
730 {
731 struct mmc_config *cfg = &host->plat->cfg;
732
733 cfg->f_max = host->max_clk;
734 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
735 cfg->b_max = 65535;
736
737 dev_dbg(dev, "f_max %d, f_min %d\n",
738 cfg->f_max, cfg->f_min);
739
740 /* host controller capabilities */
741 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
742
743 /* report supported voltage ranges */
744 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
745
746 /* Set interrupt enables */
747 host->hcfg = SDHCFG_BUSY_IRPT_EN;
748
749 bcm2835_reset_internal(host);
750 }
751
bcm2835_probe(struct udevice * dev)752 static int bcm2835_probe(struct udevice *dev)
753 {
754 struct bcm2835_plat *plat = dev_get_platdata(dev);
755 struct bcm2835_host *host = dev_get_priv(dev);
756 struct mmc *mmc = mmc_get_mmc_dev(dev);
757 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
758
759 host->dev = dev;
760 host->mmc = mmc;
761 host->plat = plat;
762 upriv->mmc = &plat->mmc;
763 plat->cfg.name = dev->name;
764
765 host->phys_addr = devfdt_get_addr(dev);
766 if (host->phys_addr == FDT_ADDR_T_NONE)
767 return -EINVAL;
768
769 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
770 if (!host->ioaddr)
771 return -ENOMEM;
772
773 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
774
775 bcm2835_add_host(host);
776
777 dev_dbg(dev, "%s -> OK\n", __func__);
778
779 return 0;
780 }
781
782 static const struct udevice_id bcm2835_match[] = {
783 { .compatible = "brcm,bcm2835-sdhost" },
784 { }
785 };
786
787 static const struct dm_mmc_ops bcm2835_ops = {
788 .send_cmd = bcm2835_send_cmd,
789 .set_ios = bcm2835_set_ios,
790 };
791
bcm2835_bind(struct udevice * dev)792 static int bcm2835_bind(struct udevice *dev)
793 {
794 struct bcm2835_plat *plat = dev_get_platdata(dev);
795
796 return mmc_bind(dev, &plat->mmc, &plat->cfg);
797 }
798
799 U_BOOT_DRIVER(bcm2835_sdhost) = {
800 .name = "bcm2835-sdhost",
801 .id = UCLASS_MMC,
802 .of_match = bcm2835_match,
803 .bind = bcm2835_bind,
804 .probe = bcm2835_probe,
805 .priv_auto_alloc_size = sizeof(struct bcm2835_host),
806 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),
807 .ops = &bcm2835_ops,
808 };
809