1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * Copyright 2018-2019 NXP
4 *
5 * PCIe Gen4 driver for NXP Layerscape SoCs
6 * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
7 *
8 */
9
10 #include <common.h>
11 #include <pci.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/io.h>
14 #include <errno.h>
15 #ifdef CONFIG_OF_BOARD_SETUP
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
18 #ifdef CONFIG_ARM
19 #include <asm/arch/clock.h>
20 #endif
21 #include "pcie_layerscape_gen4.h"
22
23 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
24 /*
25 * Return next available LUT index.
26 */
ls_pcie_g4_next_lut_index(struct ls_pcie_g4 * pcie)27 static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
28 {
29 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
30 return pcie->next_lut_index++;
31
32 return -ENOSPC; /* LUT is full */
33 }
34
35 /* returns the next available streamid for pcie, -errno if failed */
ls_pcie_g4_next_streamid(struct ls_pcie_g4 * pcie)36 static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
37 {
38 int stream_id = pcie->stream_id_cur;
39
40 if (stream_id > FSL_PEX_STREAM_ID_NUM)
41 return -EINVAL;
42
43 pcie->stream_id_cur++;
44
45 return stream_id | ((pcie->idx + 1) << 11);
46 }
47
48 /*
49 * Program a single LUT entry
50 */
ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 * pcie,int index,u32 devid,u32 streamid)51 static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
52 u32 devid, u32 streamid)
53 {
54 /* leave mask as all zeroes, want to match all bits */
55 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
56 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
57 }
58
59 /*
60 * An msi-map is a property to be added to the pci controller
61 * node. It is a table, where each entry consists of 4 fields
62 * e.g.:
63 *
64 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
65 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
66 */
fdt_pcie_set_msi_map_entry(void * blob,struct ls_pcie_g4 * pcie,u32 devid,u32 streamid)67 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
68 u32 devid, u32 streamid)
69 {
70 u32 *prop;
71 u32 phandle;
72 int nodeoff;
73
74 #ifdef CONFIG_FSL_PCIE_COMPAT
75 nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
76 pcie->ccsr_res.start);
77 #else
78 #error "No CONFIG_FSL_PCIE_COMPAT defined"
79 #endif
80 if (nodeoff < 0) {
81 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
82 return;
83 }
84
85 /* get phandle to MSI controller */
86 prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
87 if (!prop) {
88 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
89 __func__, pcie->idx);
90 return;
91 }
92 phandle = fdt32_to_cpu(*prop);
93
94 /* set one msi-map row */
95 fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
96 fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
97 fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
98 fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
99 }
100
101 /*
102 * An iommu-map is a property to be added to the pci controller
103 * node. It is a table, where each entry consists of 4 fields
104 * e.g.:
105 *
106 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
107 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
108 */
fdt_pcie_set_iommu_map_entry(void * blob,struct ls_pcie_g4 * pcie,u32 devid,u32 streamid)109 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,
110 u32 devid, u32 streamid)
111 {
112 u32 *prop;
113 u32 iommu_map[4];
114 int nodeoff;
115 int lenp;
116
117 #ifdef CONFIG_FSL_PCIE_COMPAT
118 nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
119 pcie->ccsr_res.start);
120 #else
121 #error "No CONFIG_FSL_PCIE_COMPAT defined"
122 #endif
123 if (nodeoff < 0) {
124 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
125 return;
126 }
127
128 /* get phandle to iommu controller */
129 prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
130 if (!prop) {
131 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
132 __func__, pcie->idx);
133 return;
134 }
135
136 /* set iommu-map row */
137 iommu_map[0] = cpu_to_fdt32(devid);
138 iommu_map[1] = *++prop;
139 iommu_map[2] = cpu_to_fdt32(streamid);
140 iommu_map[3] = cpu_to_fdt32(1);
141
142 if (devid == 0)
143 fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
144 else
145 fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
146 }
147
fdt_fixup_pcie(void * blob)148 static void fdt_fixup_pcie(void *blob)
149 {
150 struct udevice *dev, *bus;
151 struct ls_pcie_g4 *pcie;
152 int streamid;
153 int index;
154 pci_dev_t bdf;
155
156 /* Scan all known buses */
157 for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
158 for (bus = dev; device_is_on_pci_bus(bus);)
159 bus = bus->parent;
160 pcie = dev_get_priv(bus);
161
162 streamid = ls_pcie_g4_next_streamid(pcie);
163 if (streamid < 0) {
164 debug("ERROR: no stream ids free\n");
165 continue;
166 }
167
168 index = ls_pcie_g4_next_lut_index(pcie);
169 if (index < 0) {
170 debug("ERROR: no LUT indexes free\n");
171 continue;
172 }
173
174 /* the DT fixup must be relative to the hose first_busno */
175 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
176 /* map PCI b.d.f to streamID in LUT */
177 ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
178 /* update msi-map in device tree */
179 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid);
180 /* update iommu-map in device tree */
181 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, streamid);
182 }
183 }
184 #endif
185
ft_pcie_ep_layerscape_gen4_fix(void * blob,struct ls_pcie_g4 * pcie)186 static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
187 {
188 int off;
189
190 off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
191 pcie->ccsr_res.start);
192
193 if (off < 0) {
194 debug("%s: ERROR: failed to find pcie compatiable\n",
195 __func__);
196 return;
197 }
198
199 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
200 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
201 else
202 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
203 }
204
ft_pcie_rc_layerscape_gen4_fix(void * blob,struct ls_pcie_g4 * pcie)205 static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
206 {
207 int off;
208
209 #ifdef CONFIG_FSL_PCIE_COMPAT
210 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
211 pcie->ccsr_res.start);
212 #else
213 #error "No CONFIG_FSL_PCIE_COMPAT defined"
214 #endif
215 if (off < 0) {
216 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
217 return;
218 }
219
220 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
221 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
222 else
223 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
224 }
225
ft_pcie_layerscape_gen4_setup(void * blob,struct ls_pcie_g4 * pcie)226 static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
227 {
228 ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
229 ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
230 }
231
232 /* Fixup Kernel DT for PCIe */
ft_pci_setup(void * blob,bd_t * bd)233 void ft_pci_setup(void *blob, bd_t *bd)
234 {
235 struct ls_pcie_g4 *pcie;
236
237 list_for_each_entry(pcie, &ls_pcie_g4_list, list)
238 ft_pcie_layerscape_gen4_setup(blob, pcie);
239
240 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
241 fdt_fixup_pcie(blob);
242 #endif
243 }
244
245 #else /* !CONFIG_OF_BOARD_SETUP */
ft_pci_setup(void * blob,bd_t * bd)246 void ft_pci_setup(void *blob, bd_t *bd)
247 {
248 }
249 #endif
250