1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 *
5 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
6 * based on Linux driver : pinctrl/pinctrl-stmfx.c
7 */
8 #include <common.h>
9 #include <dm.h>
10 #include <i2c.h>
11 #include <asm/gpio.h>
12 #include <dm/device.h>
13 #include <dm/device-internal.h>
14 #include <dm/lists.h>
15 #include <dm/pinctrl.h>
16 #include <linux/bitfield.h>
17 #include <power/regulator.h>
18
19 /* STMFX pins = GPIO[15:0] + aGPIO[7:0] */
20 #define STMFX_MAX_GPIO 16
21 #define STMFX_MAX_AGPIO 8
22
23 /* General */
24 #define STMFX_REG_CHIP_ID 0x00 /* R */
25 #define STMFX_REG_FW_VERSION_MSB 0x01 /* R */
26 #define STMFX_REG_FW_VERSION_LSB 0x02 /* R */
27 #define STMFX_REG_SYS_CTRL 0x40 /* RW */
28
29 /* MFX boot time is around 10ms, so after reset, we have to wait this delay */
30 #define STMFX_BOOT_TIME_MS 10
31
32 /* GPIOs expander */
33 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
34 #define STMFX_REG_GPIO_STATE 0x10 /* R */
35 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
36 #define STMFX_REG_GPIO_DIR 0x60 /* RW */
37 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
38 #define STMFX_REG_GPIO_TYPE 0x64 /* RW */
39 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
40 #define STMFX_REG_GPIO_PUPD 0x68 /* RW */
41 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
42 #define STMFX_REG_GPO_SET 0x6C /* RW */
43 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
44 #define STMFX_REG_GPO_CLR 0x70 /* RW */
45
46 /* STMFX_REG_CHIP_ID bitfields */
47 #define STMFX_REG_CHIP_ID_MASK GENMASK(7, 0)
48
49 /* STMFX_REG_SYS_CTRL bitfields */
50 #define STMFX_REG_SYS_CTRL_GPIO_EN BIT(0)
51 #define STMFX_REG_SYS_CTRL_ALTGPIO_EN BIT(3)
52 #define STMFX_REG_SYS_CTRL_SWRST BIT(7)
53
54 #define NR_GPIO_REGS 3
55 #define NR_GPIOS_PER_REG 8
56 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
57 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
58 #define get_mask(offset) (BIT(get_shift(offset)))
59
60 struct stmfx_pinctrl {
61 struct udevice *gpio;
62 };
63
stmfx_read(struct udevice * dev,uint offset)64 static int stmfx_read(struct udevice *dev, uint offset)
65 {
66 return dm_i2c_reg_read(dev_get_parent(dev), offset);
67 }
68
stmfx_write(struct udevice * dev,uint offset,unsigned int val)69 static int stmfx_write(struct udevice *dev, uint offset, unsigned int val)
70 {
71 return dm_i2c_reg_write(dev_get_parent(dev), offset, val);
72 }
73
stmfx_gpio_get(struct udevice * dev,unsigned int offset)74 static int stmfx_gpio_get(struct udevice *dev, unsigned int offset)
75 {
76 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
77 u32 mask = get_mask(offset);
78 int ret;
79
80 ret = stmfx_read(dev, reg);
81
82 return ret < 0 ? ret : !!(ret & mask);
83 }
84
stmfx_gpio_set(struct udevice * dev,unsigned int offset,int value)85 static int stmfx_gpio_set(struct udevice *dev, unsigned int offset, int value)
86 {
87 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
88 u32 mask = get_mask(offset);
89
90 return stmfx_write(dev, reg + get_reg(offset), mask);
91 }
92
stmfx_gpio_get_function(struct udevice * dev,unsigned int offset)93 static int stmfx_gpio_get_function(struct udevice *dev, unsigned int offset)
94 {
95 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
96 u32 mask = get_mask(offset);
97 int ret;
98
99 ret = stmfx_read(dev, reg);
100
101 if (ret < 0)
102 return ret;
103 /* On stmfx, gpio pins direction is (0)input, (1)output. */
104
105 return ret & mask ? GPIOF_OUTPUT : GPIOF_INPUT;
106 }
107
stmfx_gpio_direction_input(struct udevice * dev,unsigned int offset)108 static int stmfx_gpio_direction_input(struct udevice *dev, unsigned int offset)
109 {
110 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
111 u32 mask = get_mask(offset);
112 int ret;
113
114 ret = stmfx_read(dev, reg);
115 if (ret < 0)
116 return ret;
117
118 ret &= ~mask;
119
120 return stmfx_write(dev, reg, ret & ~mask);
121 }
122
stmfx_gpio_direction_output(struct udevice * dev,unsigned int offset,int value)123 static int stmfx_gpio_direction_output(struct udevice *dev,
124 unsigned int offset, int value)
125 {
126 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
127 u32 mask = get_mask(offset);
128 int ret;
129
130 ret = stmfx_gpio_set(dev, offset, value);
131 if (ret < 0)
132 return ret;
133
134 ret = stmfx_read(dev, reg);
135 if (ret < 0)
136 return ret;
137
138 return stmfx_write(dev, reg, ret | mask);
139 }
140
stmfx_gpio_probe(struct udevice * dev)141 static int stmfx_gpio_probe(struct udevice *dev)
142 {
143 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
144 struct ofnode_phandle_args args;
145 u8 sys_ctrl;
146
147 uc_priv->bank_name = "stmfx";
148 uc_priv->gpio_count = STMFX_MAX_GPIO + STMFX_MAX_AGPIO;
149 if (!dev_read_phandle_with_args(dev, "gpio-ranges",
150 NULL, 3, 0, &args)) {
151 uc_priv->gpio_count = args.args[2];
152 }
153
154 /* enable GPIO function */
155 sys_ctrl = STMFX_REG_SYS_CTRL_GPIO_EN;
156 if (uc_priv->gpio_count > STMFX_MAX_GPIO)
157 sys_ctrl |= STMFX_REG_SYS_CTRL_ALTGPIO_EN;
158 stmfx_write(dev, STMFX_REG_SYS_CTRL, sys_ctrl);
159
160 return 0;
161 }
162
163 static const struct dm_gpio_ops stmfx_gpio_ops = {
164 .set_value = stmfx_gpio_set,
165 .get_value = stmfx_gpio_get,
166 .get_function = stmfx_gpio_get_function,
167 .direction_input = stmfx_gpio_direction_input,
168 .direction_output = stmfx_gpio_direction_output,
169 };
170
171 U_BOOT_DRIVER(stmfx_gpio) = {
172 .name = "stmfx-gpio",
173 .id = UCLASS_GPIO,
174 .probe = stmfx_gpio_probe,
175 .ops = &stmfx_gpio_ops,
176 };
177
178 #if CONFIG_IS_ENABLED(PINCONF)
179 static const struct pinconf_param stmfx_pinctrl_conf_params[] = {
180 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
181 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 },
182 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 },
183 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 },
184 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
185 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
186 { "output-high", PIN_CONFIG_OUTPUT, 1 },
187 { "output-low", PIN_CONFIG_OUTPUT, 0 },
188 };
189
stmfx_pinctrl_set_pupd(struct udevice * dev,unsigned int pin,u32 pupd)190 static int stmfx_pinctrl_set_pupd(struct udevice *dev,
191 unsigned int pin, u32 pupd)
192 {
193 u8 reg = STMFX_REG_GPIO_PUPD + get_reg(pin);
194 u32 mask = get_mask(pin);
195 int ret;
196
197 ret = stmfx_read(dev, reg);
198 if (ret < 0)
199 return ret;
200 ret = (ret & ~mask) | (pupd ? mask : 0);
201
202 return stmfx_write(dev, reg, ret);
203 }
204
stmfx_pinctrl_set_type(struct udevice * dev,unsigned int pin,u32 type)205 static int stmfx_pinctrl_set_type(struct udevice *dev,
206 unsigned int pin, u32 type)
207 {
208 u8 reg = STMFX_REG_GPIO_TYPE + get_reg(pin);
209 u32 mask = get_mask(pin);
210 int ret;
211
212 ret = stmfx_read(dev, reg);
213 if (ret < 0)
214 return ret;
215 ret = (ret & ~mask) | (type ? mask : 0);
216
217 return stmfx_write(dev, reg, ret);
218 }
219
stmfx_pinctrl_conf_set(struct udevice * dev,unsigned int pin,unsigned int param,unsigned int arg)220 static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
221 unsigned int param, unsigned int arg)
222 {
223 int ret, dir;
224 struct stmfx_pinctrl *plat = dev_get_platdata(dev);
225
226 dir = stmfx_gpio_get_function(plat->gpio, pin);
227
228 if (dir < 0)
229 return dir;
230
231 switch (param) {
232 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
233 case PIN_CONFIG_BIAS_DISABLE:
234 case PIN_CONFIG_DRIVE_PUSH_PULL:
235 ret = stmfx_pinctrl_set_type(dev, pin, 0);
236 break;
237 case PIN_CONFIG_BIAS_PULL_DOWN:
238 ret = stmfx_pinctrl_set_type(dev, pin, 1);
239 if (ret)
240 return ret;
241 ret = stmfx_pinctrl_set_pupd(dev, pin, 0);
242 break;
243 case PIN_CONFIG_BIAS_PULL_UP:
244 ret = stmfx_pinctrl_set_type(dev, pin, 1);
245 if (ret)
246 return ret;
247 ret = stmfx_pinctrl_set_pupd(dev, pin, 1);
248 break;
249 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
250 ret = stmfx_pinctrl_set_type(dev, pin, 1);
251 break;
252 case PIN_CONFIG_OUTPUT:
253 ret = stmfx_gpio_direction_output(plat->gpio, pin, arg);
254 break;
255 default:
256 return -ENOTSUPP;
257 }
258
259 return ret;
260 }
261 #endif
262
stmfx_pinctrl_get_pins_count(struct udevice * dev)263 static int stmfx_pinctrl_get_pins_count(struct udevice *dev)
264 {
265 struct stmfx_pinctrl *plat = dev_get_platdata(dev);
266 struct gpio_dev_priv *uc_priv;
267
268 uc_priv = dev_get_uclass_priv(plat->gpio);
269
270 return uc_priv->gpio_count;
271 }
272
273 /*
274 * STMFX pins[15:0] are called "gpio[15:0]"
275 * and STMFX pins[23:16] are called "agpio[7:0]"
276 */
277 #define MAX_PIN_NAME_LEN 7
278 static char pin_name[MAX_PIN_NAME_LEN];
stmfx_pinctrl_get_pin_name(struct udevice * dev,unsigned int selector)279 static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev,
280 unsigned int selector)
281 {
282 if (selector < STMFX_MAX_GPIO)
283 snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
284 else
285 snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16);
286 return pin_name;
287 }
288
stmfx_pinctrl_get_pin_muxing(struct udevice * dev,unsigned int selector,char * buf,int size)289 static int stmfx_pinctrl_get_pin_muxing(struct udevice *dev,
290 unsigned int selector,
291 char *buf, int size)
292 {
293 struct stmfx_pinctrl *plat = dev_get_platdata(dev);
294 int func;
295
296 func = stmfx_gpio_get_function(plat->gpio, selector);
297 if (func < 0)
298 return func;
299
300 snprintf(buf, size, "%s", func == GPIOF_INPUT ? "input" : "output");
301
302 return 0;
303 }
304
stmfx_pinctrl_bind(struct udevice * dev)305 static int stmfx_pinctrl_bind(struct udevice *dev)
306 {
307 struct stmfx_pinctrl *plat = dev_get_platdata(dev);
308
309 return device_bind_driver_to_node(dev->parent,
310 "stmfx-gpio", "stmfx-gpio",
311 dev_ofnode(dev), &plat->gpio);
312 };
313
stmfx_pinctrl_probe(struct udevice * dev)314 static int stmfx_pinctrl_probe(struct udevice *dev)
315 {
316 struct stmfx_pinctrl *plat = dev_get_platdata(dev);
317
318 return device_probe(plat->gpio);
319 };
320
321 const struct pinctrl_ops stmfx_pinctrl_ops = {
322 .get_pins_count = stmfx_pinctrl_get_pins_count,
323 .get_pin_name = stmfx_pinctrl_get_pin_name,
324 .set_state = pinctrl_generic_set_state,
325 .get_pin_muxing = stmfx_pinctrl_get_pin_muxing,
326 #if CONFIG_IS_ENABLED(PINCONF)
327 .pinconf_set = stmfx_pinctrl_conf_set,
328 .pinconf_num_params = ARRAY_SIZE(stmfx_pinctrl_conf_params),
329 .pinconf_params = stmfx_pinctrl_conf_params,
330 #endif
331 };
332
333 static const struct udevice_id stmfx_pinctrl_match[] = {
334 { .compatible = "st,stmfx-0300-pinctrl", },
335 };
336
337 U_BOOT_DRIVER(stmfx_pinctrl) = {
338 .name = "stmfx-pinctrl",
339 .id = UCLASS_PINCTRL,
340 .of_match = of_match_ptr(stmfx_pinctrl_match),
341 .bind = stmfx_pinctrl_bind,
342 .probe = stmfx_pinctrl_probe,
343 .ops = &stmfx_pinctrl_ops,
344 .platdata_auto_alloc_size = sizeof(struct stmfx_pinctrl),
345 };
346
stmfx_chip_init(struct udevice * dev)347 static int stmfx_chip_init(struct udevice *dev)
348 {
349 u8 id;
350 u8 version[2];
351 int ret;
352 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
353
354 id = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
355 if (id < 0) {
356 dev_err(dev, "error reading chip id: %d\n", id);
357 return ret;
358 }
359 /*
360 * Check that ID is the complement of the I2C address:
361 * STMFX I2C address follows the 7-bit format (MSB), that's why
362 * client->addr is shifted.
363 *
364 * STMFX_I2C_ADDR| STMFX | Linux
365 * input pin | I2C device address | I2C device address
366 *---------------------------------------------------------
367 * 0 | b: 1000 010x h:0x84 | 0x42
368 * 1 | b: 1000 011x h:0x86 | 0x43
369 */
370 if (FIELD_GET(STMFX_REG_CHIP_ID_MASK, ~id) != (chip->chip_addr << 1)) {
371 dev_err(dev, "unknown chip id: %#x\n", id);
372 return -EINVAL;
373 }
374
375 ret = dm_i2c_read(dev, STMFX_REG_FW_VERSION_MSB,
376 version, sizeof(version));
377 if (ret) {
378 dev_err(dev, "error reading fw version: %d\n", ret);
379 return ret;
380 }
381
382 dev_info(dev, "STMFX id: %#x, fw version: %x.%02x\n",
383 id, version[0], version[1]);
384
385 ret = dm_i2c_reg_read(dev, STMFX_REG_SYS_CTRL);
386
387 if (ret < 0)
388 return ret;
389
390 ret = dm_i2c_reg_write(dev, STMFX_REG_SYS_CTRL,
391 ret | STMFX_REG_SYS_CTRL_SWRST);
392 if (ret)
393 return ret;
394
395 mdelay(STMFX_BOOT_TIME_MS);
396
397 return ret;
398 }
399
stmfx_probe(struct udevice * dev)400 static int stmfx_probe(struct udevice *dev)
401 {
402 struct udevice *vdd;
403 int ret;
404
405 ret = device_get_supply_regulator(dev, "vdd-supply", &vdd);
406 if (ret && ret != -ENOENT) {
407 dev_err(dev, "vdd regulator error:%d\n", ret);
408 return ret;
409 }
410 if (!ret) {
411 ret = regulator_set_enable(vdd, true);
412 if (ret) {
413 dev_err(dev, "vdd enable failed: %d\n", ret);
414 return ret;
415 }
416 }
417
418 return stmfx_chip_init(dev);
419 }
420
421 static const struct udevice_id stmfx_match[] = {
422 { .compatible = "st,stmfx-0300", },
423 };
424
425 U_BOOT_DRIVER(stmfx) = {
426 .name = "stmfx",
427 .id = UCLASS_I2C_GENERIC,
428 .of_match = of_match_ptr(stmfx_match),
429 .probe = stmfx_probe,
430 .bind = dm_scan_fdt_dev,
431 };
432