1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Designware master SPI core controller driver
4 *
5 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 *
7 * Very loosely based on the Linux driver:
8 * drivers/spi/spi-dw.c, which is:
9 * Copyright (c) 2009, Intel Corporation.
10 */
11
12 #include <common.h>
13 #include <asm-generic/gpio.h>
14 #include <clk.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <malloc.h>
18 #include <spi.h>
19 #include <fdtdec.h>
20 #include <reset.h>
21 #include <linux/compat.h>
22 #include <linux/iopoll.h>
23 #include <asm/io.h>
24
25 /* Register offsets */
26 #define DW_SPI_CTRL0 0x00
27 #define DW_SPI_CTRL1 0x04
28 #define DW_SPI_SSIENR 0x08
29 #define DW_SPI_MWCR 0x0c
30 #define DW_SPI_SER 0x10
31 #define DW_SPI_BAUDR 0x14
32 #define DW_SPI_TXFLTR 0x18
33 #define DW_SPI_RXFLTR 0x1c
34 #define DW_SPI_TXFLR 0x20
35 #define DW_SPI_RXFLR 0x24
36 #define DW_SPI_SR 0x28
37 #define DW_SPI_IMR 0x2c
38 #define DW_SPI_ISR 0x30
39 #define DW_SPI_RISR 0x34
40 #define DW_SPI_TXOICR 0x38
41 #define DW_SPI_RXOICR 0x3c
42 #define DW_SPI_RXUICR 0x40
43 #define DW_SPI_MSTICR 0x44
44 #define DW_SPI_ICR 0x48
45 #define DW_SPI_DMACR 0x4c
46 #define DW_SPI_DMATDLR 0x50
47 #define DW_SPI_DMARDLR 0x54
48 #define DW_SPI_IDR 0x58
49 #define DW_SPI_VERSION 0x5c
50 #define DW_SPI_DR 0x60
51
52 /* Bit fields in CTRLR0 */
53 #define SPI_DFS_OFFSET 0
54
55 #define SPI_FRF_OFFSET 4
56 #define SPI_FRF_SPI 0x0
57 #define SPI_FRF_SSP 0x1
58 #define SPI_FRF_MICROWIRE 0x2
59 #define SPI_FRF_RESV 0x3
60
61 #define SPI_MODE_OFFSET 6
62 #define SPI_SCPH_OFFSET 6
63 #define SPI_SCOL_OFFSET 7
64
65 #define SPI_TMOD_OFFSET 8
66 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
67 #define SPI_TMOD_TR 0x0 /* xmit & recv */
68 #define SPI_TMOD_TO 0x1 /* xmit only */
69 #define SPI_TMOD_RO 0x2 /* recv only */
70 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
71
72 #define SPI_SLVOE_OFFSET 10
73 #define SPI_SRL_OFFSET 11
74 #define SPI_CFS_OFFSET 12
75
76 /* Bit fields in SR, 7 bits */
77 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
78 #define SR_BUSY BIT(0)
79 #define SR_TF_NOT_FULL BIT(1)
80 #define SR_TF_EMPT BIT(2)
81 #define SR_RF_NOT_EMPT BIT(3)
82 #define SR_RF_FULL BIT(4)
83 #define SR_TX_ERR BIT(5)
84 #define SR_DCOL BIT(6)
85
86 #define RX_TIMEOUT 1000 /* timeout in ms */
87
88 struct dw_spi_platdata {
89 s32 frequency; /* Default clock frequency, -1 for none */
90 void __iomem *regs;
91 };
92
93 struct dw_spi_priv {
94 void __iomem *regs;
95 unsigned int freq; /* Default frequency */
96 unsigned int mode;
97 struct clk clk;
98 unsigned long bus_clk_rate;
99
100 struct gpio_desc cs_gpio; /* External chip-select gpio */
101
102 int bits_per_word;
103 u8 cs; /* chip select pin */
104 u8 tmode; /* TR/TO/RO/EEPROM */
105 u8 type; /* SPI/SSP/MicroWire */
106 int len;
107
108 u32 fifo_len; /* depth of the FIFO buffer */
109 void *tx;
110 void *tx_end;
111 void *rx;
112 void *rx_end;
113
114 struct reset_ctl_bulk resets;
115 };
116
dw_read(struct dw_spi_priv * priv,u32 offset)117 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
118 {
119 return __raw_readl(priv->regs + offset);
120 }
121
dw_write(struct dw_spi_priv * priv,u32 offset,u32 val)122 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
123 {
124 __raw_writel(val, priv->regs + offset);
125 }
126
request_gpio_cs(struct udevice * bus)127 static int request_gpio_cs(struct udevice *bus)
128 {
129 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
130 struct dw_spi_priv *priv = dev_get_priv(bus);
131 int ret;
132
133 /* External chip select gpio line is optional */
134 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
135 if (ret == -ENOENT)
136 return 0;
137
138 if (ret < 0) {
139 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
140 return ret;
141 }
142
143 if (dm_gpio_is_valid(&priv->cs_gpio)) {
144 dm_gpio_set_dir_flags(&priv->cs_gpio,
145 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
146 }
147
148 debug("%s: used external gpio for CS management\n", __func__);
149 #endif
150 return 0;
151 }
152
dw_spi_ofdata_to_platdata(struct udevice * bus)153 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
154 {
155 struct dw_spi_platdata *plat = bus->platdata;
156
157 plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
158
159 /* Use 500KHz as a suitable default */
160 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
161 500000);
162 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
163 plat->frequency);
164
165 return request_gpio_cs(bus);
166 }
167
spi_enable_chip(struct dw_spi_priv * priv,int enable)168 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
169 {
170 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
171 }
172
173 /* Restart the controller, disable all interrupts, clean rx fifo */
spi_hw_init(struct dw_spi_priv * priv)174 static void spi_hw_init(struct dw_spi_priv *priv)
175 {
176 spi_enable_chip(priv, 0);
177 dw_write(priv, DW_SPI_IMR, 0xff);
178 spi_enable_chip(priv, 1);
179
180 /*
181 * Try to detect the FIFO depth if not set by interface driver,
182 * the depth could be from 2 to 256 from HW spec
183 */
184 if (!priv->fifo_len) {
185 u32 fifo;
186
187 for (fifo = 1; fifo < 256; fifo++) {
188 dw_write(priv, DW_SPI_TXFLTR, fifo);
189 if (fifo != dw_read(priv, DW_SPI_TXFLTR))
190 break;
191 }
192
193 priv->fifo_len = (fifo == 1) ? 0 : fifo;
194 dw_write(priv, DW_SPI_TXFLTR, 0);
195 }
196 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
197 }
198
199 /*
200 * We define dw_spi_get_clk function as 'weak' as some targets
201 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
202 * and implement dw_spi_get_clk their own way in their clock manager.
203 */
dw_spi_get_clk(struct udevice * bus,ulong * rate)204 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
205 {
206 struct dw_spi_priv *priv = dev_get_priv(bus);
207 int ret;
208
209 ret = clk_get_by_index(bus, 0, &priv->clk);
210 if (ret)
211 return ret;
212
213 ret = clk_enable(&priv->clk);
214 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
215 return ret;
216
217 *rate = clk_get_rate(&priv->clk);
218 if (!*rate)
219 goto err_rate;
220
221 debug("%s: get spi controller clk via device tree: %lu Hz\n",
222 __func__, *rate);
223
224 return 0;
225
226 err_rate:
227 clk_disable(&priv->clk);
228 clk_free(&priv->clk);
229
230 return -EINVAL;
231 }
232
dw_spi_reset(struct udevice * bus)233 static int dw_spi_reset(struct udevice *bus)
234 {
235 int ret;
236 struct dw_spi_priv *priv = dev_get_priv(bus);
237
238 ret = reset_get_bulk(bus, &priv->resets);
239 if (ret) {
240 /*
241 * Return 0 if error due to !CONFIG_DM_RESET and reset
242 * DT property is not present.
243 */
244 if (ret == -ENOENT || ret == -ENOTSUPP)
245 return 0;
246
247 dev_warn(bus, "Can't get reset: %d\n", ret);
248 return ret;
249 }
250
251 ret = reset_deassert_bulk(&priv->resets);
252 if (ret) {
253 reset_release_bulk(&priv->resets);
254 dev_err(bus, "Failed to reset: %d\n", ret);
255 return ret;
256 }
257
258 return 0;
259 }
260
dw_spi_probe(struct udevice * bus)261 static int dw_spi_probe(struct udevice *bus)
262 {
263 struct dw_spi_platdata *plat = dev_get_platdata(bus);
264 struct dw_spi_priv *priv = dev_get_priv(bus);
265 int ret;
266
267 priv->regs = plat->regs;
268 priv->freq = plat->frequency;
269
270 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
271 if (ret)
272 return ret;
273
274 ret = dw_spi_reset(bus);
275 if (ret)
276 return ret;
277
278 /* Currently only bits_per_word == 8 supported */
279 priv->bits_per_word = 8;
280
281 priv->tmode = 0; /* Tx & Rx */
282
283 /* Basic HW init */
284 spi_hw_init(priv);
285
286 return 0;
287 }
288
289 /* Return the max entries we can fill into tx fifo */
tx_max(struct dw_spi_priv * priv)290 static inline u32 tx_max(struct dw_spi_priv *priv)
291 {
292 u32 tx_left, tx_room, rxtx_gap;
293
294 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
295 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
296
297 /*
298 * Another concern is about the tx/rx mismatch, we
299 * thought about using (priv->fifo_len - rxflr - txflr) as
300 * one maximum value for tx, but it doesn't cover the
301 * data which is out of tx/rx fifo and inside the
302 * shift registers. So a control from sw point of
303 * view is taken.
304 */
305 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
306 (priv->bits_per_word >> 3);
307
308 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
309 }
310
311 /* Return the max entries we should read out of rx fifo */
rx_max(struct dw_spi_priv * priv)312 static inline u32 rx_max(struct dw_spi_priv *priv)
313 {
314 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
315
316 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
317 }
318
dw_writer(struct dw_spi_priv * priv)319 static void dw_writer(struct dw_spi_priv *priv)
320 {
321 u32 max = tx_max(priv);
322 u16 txw = 0;
323
324 while (max--) {
325 /* Set the tx word if the transfer's original "tx" is not null */
326 if (priv->tx_end - priv->len) {
327 if (priv->bits_per_word == 8)
328 txw = *(u8 *)(priv->tx);
329 else
330 txw = *(u16 *)(priv->tx);
331 }
332 dw_write(priv, DW_SPI_DR, txw);
333 debug("%s: tx=0x%02x\n", __func__, txw);
334 priv->tx += priv->bits_per_word >> 3;
335 }
336 }
337
dw_reader(struct dw_spi_priv * priv)338 static void dw_reader(struct dw_spi_priv *priv)
339 {
340 u32 max = rx_max(priv);
341 u16 rxw;
342
343 while (max--) {
344 rxw = dw_read(priv, DW_SPI_DR);
345 debug("%s: rx=0x%02x\n", __func__, rxw);
346
347 /* Care about rx if the transfer's original "rx" is not null */
348 if (priv->rx_end - priv->len) {
349 if (priv->bits_per_word == 8)
350 *(u8 *)(priv->rx) = rxw;
351 else
352 *(u16 *)(priv->rx) = rxw;
353 }
354 priv->rx += priv->bits_per_word >> 3;
355 }
356 }
357
poll_transfer(struct dw_spi_priv * priv)358 static int poll_transfer(struct dw_spi_priv *priv)
359 {
360 do {
361 dw_writer(priv);
362 dw_reader(priv);
363 } while (priv->rx_end > priv->rx);
364
365 return 0;
366 }
367
368 /*
369 * We define external_cs_manage function as 'weak' as some targets
370 * (like MSCC Ocelot) don't control the external CS pin using a GPIO
371 * controller. These SoCs use specific registers to control by
372 * software the SPI pins (and especially the CS).
373 */
external_cs_manage(struct udevice * dev,bool on)374 __weak void external_cs_manage(struct udevice *dev, bool on)
375 {
376 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
377 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
378
379 if (!dm_gpio_is_valid(&priv->cs_gpio))
380 return;
381
382 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
383 #endif
384 }
385
dw_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)386 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
387 const void *dout, void *din, unsigned long flags)
388 {
389 struct udevice *bus = dev->parent;
390 struct dw_spi_priv *priv = dev_get_priv(bus);
391 const u8 *tx = dout;
392 u8 *rx = din;
393 int ret = 0;
394 u32 cr0 = 0;
395 u32 val;
396 u32 cs;
397
398 /* spi core configured to do 8 bit transfers */
399 if (bitlen % 8) {
400 debug("Non byte aligned SPI transfer.\n");
401 return -1;
402 }
403
404 /* Start the transaction if necessary. */
405 if (flags & SPI_XFER_BEGIN)
406 external_cs_manage(dev, false);
407
408 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
409 (priv->mode << SPI_MODE_OFFSET) |
410 (priv->tmode << SPI_TMOD_OFFSET);
411
412 if (rx && tx)
413 priv->tmode = SPI_TMOD_TR;
414 else if (rx)
415 priv->tmode = SPI_TMOD_RO;
416 else
417 /*
418 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
419 * any data which breaks our logic in poll_transfer() above.
420 */
421 priv->tmode = SPI_TMOD_TR;
422
423 cr0 &= ~SPI_TMOD_MASK;
424 cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
425
426 priv->len = bitlen >> 3;
427 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
428
429 priv->tx = (void *)tx;
430 priv->tx_end = priv->tx + priv->len;
431 priv->rx = rx;
432 priv->rx_end = priv->rx + priv->len;
433
434 /* Disable controller before writing control registers */
435 spi_enable_chip(priv, 0);
436
437 debug("%s: cr0=%08x\n", __func__, cr0);
438 /* Reprogram cr0 only if changed */
439 if (dw_read(priv, DW_SPI_CTRL0) != cr0)
440 dw_write(priv, DW_SPI_CTRL0, cr0);
441
442 /*
443 * Configure the desired SS (slave select 0...3) in the controller
444 * The DW SPI controller will activate and deactivate this CS
445 * automatically. So no cs_activate() etc is needed in this driver.
446 */
447 cs = spi_chip_select(dev);
448 dw_write(priv, DW_SPI_SER, 1 << cs);
449
450 /* Enable controller after writing control registers */
451 spi_enable_chip(priv, 1);
452
453 /* Start transfer in a polling loop */
454 ret = poll_transfer(priv);
455
456 /*
457 * Wait for current transmit operation to complete.
458 * Otherwise if some data still exists in Tx FIFO it can be
459 * silently flushed, i.e. dropped on disabling of the controller,
460 * which happens when writing 0 to DW_SPI_SSIENR which happens
461 * in the beginning of new transfer.
462 */
463 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
464 (val & SR_TF_EMPT) && !(val & SR_BUSY),
465 RX_TIMEOUT * 1000)) {
466 ret = -ETIMEDOUT;
467 }
468
469 /* Stop the transaction if necessary */
470 if (flags & SPI_XFER_END)
471 external_cs_manage(dev, true);
472
473 return ret;
474 }
475
dw_spi_set_speed(struct udevice * bus,uint speed)476 static int dw_spi_set_speed(struct udevice *bus, uint speed)
477 {
478 struct dw_spi_platdata *plat = bus->platdata;
479 struct dw_spi_priv *priv = dev_get_priv(bus);
480 u16 clk_div;
481
482 if (speed > plat->frequency)
483 speed = plat->frequency;
484
485 /* Disable controller before writing control registers */
486 spi_enable_chip(priv, 0);
487
488 /* clk_div doesn't support odd number */
489 clk_div = priv->bus_clk_rate / speed;
490 clk_div = (clk_div + 1) & 0xfffe;
491 dw_write(priv, DW_SPI_BAUDR, clk_div);
492
493 /* Enable controller after writing control registers */
494 spi_enable_chip(priv, 1);
495
496 priv->freq = speed;
497 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
498 priv->freq, clk_div);
499
500 return 0;
501 }
502
dw_spi_set_mode(struct udevice * bus,uint mode)503 static int dw_spi_set_mode(struct udevice *bus, uint mode)
504 {
505 struct dw_spi_priv *priv = dev_get_priv(bus);
506
507 /*
508 * Can't set mode yet. Since this depends on if rx, tx, or
509 * rx & tx is requested. So we have to defer this to the
510 * real transfer function.
511 */
512 priv->mode = mode;
513 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
514
515 return 0;
516 }
517
dw_spi_remove(struct udevice * bus)518 static int dw_spi_remove(struct udevice *bus)
519 {
520 struct dw_spi_priv *priv = dev_get_priv(bus);
521 int ret;
522
523 ret = reset_release_bulk(&priv->resets);
524 if (ret)
525 return ret;
526
527 #if CONFIG_IS_ENABLED(CLK)
528 ret = clk_disable(&priv->clk);
529 if (ret)
530 return ret;
531
532 ret = clk_free(&priv->clk);
533 if (ret)
534 return ret;
535 #endif
536 return 0;
537 }
538
539 static const struct dm_spi_ops dw_spi_ops = {
540 .xfer = dw_spi_xfer,
541 .set_speed = dw_spi_set_speed,
542 .set_mode = dw_spi_set_mode,
543 /*
544 * cs_info is not needed, since we require all chip selects to be
545 * in the device tree explicitly
546 */
547 };
548
549 static const struct udevice_id dw_spi_ids[] = {
550 { .compatible = "snps,dw-apb-ssi" },
551 { }
552 };
553
554 U_BOOT_DRIVER(dw_spi) = {
555 .name = "dw_spi",
556 .id = UCLASS_SPI,
557 .of_match = dw_spi_ids,
558 .ops = &dw_spi_ops,
559 .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
560 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
561 .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
562 .probe = dw_spi_probe,
563 .remove = dw_spi_remove,
564 };
565