; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s

target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"

; Regression test for pr47375, in which an assertion was triggering
; because WebAssemblyTargetLowering::isVectorLoadExtDesirable was
; improperly assuming the use of simple value types.

define void @sext_vec() {
; CHECK-LABEL: sext_vec:
; CHECK:         .functype sext_vec () -> ()
; CHECK-NEXT:    .local i32
; CHECK-NEXT:  # %bb.0:
; CHECK-NEXT:    local.get 0
; CHECK-NEXT:    i32.load8_u 0
; CHECK-NEXT:    local.set 0
; CHECK-NEXT:    local.get 0
; CHECK-NEXT:    i32.const 0
; CHECK-NEXT:    i32.store8 0
; CHECK-NEXT:    local.get 0
; CHECK-NEXT:    local.get 0
; CHECK-NEXT:    local.get 0
; CHECK-NEXT:    i32.const 7
; CHECK-NEXT:    i32.shl
; CHECK-NEXT:    i32.or
; CHECK-NEXT:    i32.const 7175
; CHECK-NEXT:    i32.and
; CHECK-NEXT:    i32.store16 0
; CHECK-NEXT:    # fallthrough-return
  %L1 = load <2 x i3>, <2 x i3>* undef, align 2
  %zext = zext <2 x i3> %L1 to <2 x i10>
  store <2 x i10> %zext, <2 x i10>* undef, align 4
  ret void
}