193 .macro FETCH_ADVANCE_INST_RB reg  argument
194     add     xPC, xPC, \reg, sxtw
204 .macro FETCH reg, count
205     ldrh    \reg, [xPC, #((\count)*2)]
208 .macro FETCH_S reg, count
209     ldrsh   \reg, [xPC, #((\count)*2)]
217 .macro FETCH_B reg, count, byte
218     ldrb     \reg, [xPC, #((\count)*2+(\byte))]
224 .macro GET_INST_OPCODE reg  argument
225     and     \reg, xINST, #255
239 .macro GOTO_OPCODE reg  argument
240     add     \reg, xIBASE, \reg, lsl #${handler_size_bits}
241     br      \reg
243 .macro GOTO_OPCODE_BASE base,reg  argument
244     add     \reg, \base, \reg, lsl #${handler_size_bits}
245     br      \reg
251 .macro GET_VREG reg, vreg
252     ldr     \reg, [xFP, \vreg, uxtw #2]
254 .macro SET_VREG reg, vreg
255     str     \reg, [xFP, \vreg, uxtw #2]
258 .macro SET_VREG_OBJECT reg, vreg, tmpreg
259     str     \reg, [xFP, \vreg, uxtw #2]
260     str     \reg, [xREFS, \vreg, uxtw #2]
262 .macro SET_VREG_FLOAT reg, vreg
263     str     \reg, [xFP, \vreg, uxtw #2]
270 .macro GET_VREG_WIDE reg, vreg
272     ldr     \reg, [ip2]
274 .macro SET_VREG_WIDE reg, vreg
276     str     \reg, [ip2]
280 .macro GET_VREG_DOUBLE reg, vreg
282     ldr     \reg, [ip2]
284 .macro SET_VREG_DOUBLE reg, vreg
286     str     \reg, [ip2]
295 .macro GET_VREG_S reg, vreg
296     ldrsw   \reg, [xFP, \vreg, uxtw #2]
302 .macro VREG_INDEX_TO_ADDR reg, vreg
303     add     \reg, xFP, \vreg, uxtw #2   /* WARNING: handle shadow frame vreg zero if store */