Lines Matching refs:_mm_mullo_epi16
79 const __m128i vprod0_odd = _mm_mullo_epi16(vxi0, vxk0); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
88 const __m128i vprod1_odd = _mm_mullo_epi16(vxi1, vxk1); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
97 const __m128i vprod2_odd = _mm_mullo_epi16(vxi2, vxk2); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
106 const __m128i vprod3_odd = _mm_mullo_epi16(vxi3, vxk3); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
115 const __m128i vprod4_odd = _mm_mullo_epi16(vxi4, vxk4); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
124 const __m128i vprod5_odd = _mm_mullo_epi16(vxi5, vxk5); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
133 const __m128i vprod6_odd = _mm_mullo_epi16(vxi6, vxk6); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
142 const __m128i vprod7_odd = _mm_mullo_epi16(vxi7, vxk7); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
151 const __m128i vprod8_odd = _mm_mullo_epi16(vxi8, vxk8); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
231 const __m128i vprod0_odd = _mm_mullo_epi16(vxi0, vxk0); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
240 const __m128i vprod1_odd = _mm_mullo_epi16(vxi1, vxk1); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
249 const __m128i vprod2_odd = _mm_mullo_epi16(vxi2, vxk2); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
258 const __m128i vprod3_odd = _mm_mullo_epi16(vxi3, vxk3); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
267 const __m128i vprod4_odd = _mm_mullo_epi16(vxi4, vxk4); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
276 const __m128i vprod5_odd = _mm_mullo_epi16(vxi5, vxk5); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
285 const __m128i vprod6_odd = _mm_mullo_epi16(vxi6, vxk6); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
294 const __m128i vprod7_odd = _mm_mullo_epi16(vxi7, vxk7); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()
303 const __m128i vprod8_odd = _mm_mullo_epi16(vxi8, vxk8); in xnn_qu8_dwconv_minmax_ukernel_up8x9__sse2()