Lines Matching refs:interrupts

108 executing in EL3, or has delegated the execution to a lower EL. For interrupts,
117 interrupts. Dispatchers handling such exceptions must therefore explicitly
133 unstacked in strictly the reverse order. For interrupts, the GIC ensures this is
134 the case; for non-interrupts, the |EHF| monitors and asserts this. See
143 top-level handler for interrupts that target EL3, as described in the
147 -  On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
150    interrupts at S-EL1. Essentially, this deprecates the routing mode described
151    as :ref:`CSS=0, TEL3=0 <EL3 interrupts>`.
153    In order for S-EL1 software to handle Non-secure interrupts while having
154    |EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts
159    set to ``1`` so that *Group 0* interrupts target EL3.
162    lowest Secure priority. This means that no Non-secure interrupts can preempt
166 interrupts into distinct priority levels. A dispatcher that chooses to receive
167 interrupts can then *own* one or more priority levels, and register interrupt
179 interrupts to a priority level. In other words, all interrupts that are to
187    to use the top *n* of the 7 remaining bits to identify and assign interrupts
204 (described `later`__). The chosen priority level also determines the interrupts
233 expresses the required levels of priority. It however doesn't choose interrupts
236 The :ref:`Firmware Design guide<configuring-secure-interrupts>` explains methods
237 for configuring secure interrupts. |EHF| requires the platform to enumerate
238 interrupt properties (as opposed to just numbers) of Secure interrupts. The
239 priority of secure interrupts must match that as determined in the
291 assign interrupts to fictitious dispatchers:
331    /* List interrupt properties for GIC driver. All interrupts target EL3 */
333         /* Dispatcher 1 owns interrupts d1_0 and d1_1, so assigns priority DISP1_PRIO */
337         /* Dispatcher 2 owns interrupts d2_0 and d2_1, so assigns priority DISP2_PRIO */
341         /* Dispatcher 3 owns interrupts d3_0 and d3_1, so assigns priority DISP3_PRIO */
367 being handled: for interrupts, this is implied when the interrupt is
374 above, for interrupts, this is implied when the interrupt is EOId in the GIC;
415    panics. Also, to prevent interruption by physical interrupts of lower
418    call this when handling exceptions other than interrupts, and it needs to
426    interrupts.
457 mask—either implicitly by acknowledging Secure interrupts, or when dispatchers
458 call ``ehf_activate_priority()``. As a result, Non-secure interrupts cannot
469    Any Non-secure interrupts that become pending meanwhile cannot preempt Secure
488 For the latter case above, dispatchers before |EHF| expect Non-secure interrupts
495 When |EHF| is enabled, in order to allow Non-secure interrupts to preempt
500 .. [#irq] In case of GICv2, Non-secure interrupts while in S-EL1 were signalled
528 The following is an example flow for interrupts:
532    interrupts. This programs the appropriate priority and group (Group 0) on
533    interrupts belonging to different dispatchers.
537    interrupts. This also results in setting the routing bits in ``SCR_EL3``.
567    preventing interrupts of lower priority from preempting the handling. The
579 The GIC priority scheme, by design, prioritises Secure interrupts over Normal
583 As mentioned in `Partitioning priority levels`_, interrupts targeting distinct
587 in *Active* state), only interrupts of higher priority are signalled to the PE,
588 even if interrupts of same or lower priority are pending. This has the side
589 effect of one dispatcher being starved of interrupts by virtue of another
590 dispatcher handling its (higher priority) interrupts.
612    exception descriptor and the programmed priority of interrupts handled by the