Lines Matching refs:bakery

2099 The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2109          *                choosing its bakery number.
2110          * Bits[1 - 15] : number. This is the bakery number allocated.
2134 To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2137 for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2144 The bakery lock data structure ``bakery_info_t`` is defined for use when
2153          *                choosing its bakery number.
2154          * Bits[1 - 15] : number. This is the bakery number allocated.
2161 system represents the complete bakery lock. The view in memory for a system
2162 with n bakery locks are:
2201 Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
2206 On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
2217 There is however a performance impact for bakery locks, due to:
2220 -  Multiple cache line reads for each lock operation, since the bakery locks
2224 Measurements indicate that when bakery locks are allocated in Normal memory, the
2232 ``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can