Lines Matching refs:CSS
90 #. **CSS**. Current Security State. ``0`` when secure and ``1`` when non-secure
98 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
102 #. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in secure
106 #. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
111 #. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
118 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
125 #. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in secure
132 #. **CSS=1, TEL3=0**. Interrupt is routed to FEL when execution is in
136 #. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
146 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
156 #. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in
160 #. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
165 #. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
198 that **TEL3=1** when **CSS=0**, the FIQ bit in ``SCR_EL3`` will be programmed to
430 i.e **CSS=0, TEL3=0** & **CSS=1, TEL3=1** for Secure-EL1 interrupts
434 either security state i.e **CSS=0, TEL3=0** & **CSS=1, TEL3=0** for
439 i.e **CSS=0, TEL3=1** for non-secure interrupts. This effectively preempts
441 non-secure state. i.e **CSS=1, TEL3=0**.
509 in the routing model where **CSS=1 and TEL3=0**. Secure-EL1 interrupts
510 will be routed to EL3 (as per the routing model where **CSS=1 and
530 #. **CSS=0, TEL3=0**. If ``PSTATE.F=0``, Secure-EL1 interrupts will be
543 #. **CSS=1, TEL3=1**. Interrupts are routed to EL3 when execution is in
547 #. **CSS=0, TEL3=1**. Secure-EL1 interrupts are routed to EL3 when execution
557 #. **CSS=0, TEL3=0**. If ``PSTATE.I=0``, non-secure interrupts will be
570 #. **CSS=0, TEL3=1**. Non-secure interrupts are routed to EL3. They will not
577 #. **CSS=1, TEL3=0**. Non-secure interrupts are handled in the FEL in
840 i.e. **TEL3=1, CSS=0** and registers ``tspd_ns_interrupt_handler()`` as the
851 i.e. **TEL3=0, CSS=0**. During ``yielding`` SMC processing, the IRQ