Lines Matching refs:PSTATE

214 #. Interrupt exceptions (``PSTATE.I`` and ``F`` bits) are masked during execution
453    masks all interrupts (``PSTATE.DAIF`` bits) when it calls
530 #. **CSS=0, TEL3=0**. If ``PSTATE.F=0``, Secure-EL1 interrupts will be
534    If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
538    know the state of the system, general purpose and the ``PSTATE`` registers
548    is in secure state. They will not be visible to the SP. The ``PSTATE.F`` bit
557 #. **CSS=0, TEL3=0**. If ``PSTATE.I=0``, non-secure interrupts will be
567    If ``PSTATE.I=1`` then the non-secure interrupt will pend until execution
571    be visible to the SP. The ``PSTATE.I`` bit in Secure-EL1/Secure-EL0 will
626    ``PSTATE.I`` and ``PSTATE.F`` bits set.
852 exceptions are unmasked i.e. ``PSTATE.I=0``, and a non-secure interrupt will
899 it is generated during execution in the TSP with ``PSTATE.I`` = 0 when the
924 vector table when ``PSTATE.I`` and ``PSTATE.F`` bits are 0. As described earlier,