67 static void dump_ccu(int ap_index)  in dump_ccu()  argument
77 		win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));  in dump_ccu()
81 			alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index,  in dump_ccu()
83 			ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index,  in dump_ccu()
91 	win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index));  in dump_ccu()
114 int ccu_is_win_enabled(int ap_index, uint32_t win_id)  in ccu_is_win_enabled()  argument
116 	return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) &  in ccu_is_win_enabled()
120 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id)  in ccu_enable_win()  argument
135 	mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr);  in ccu_enable_win()
136 	mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr);  in ccu_enable_win()
141 	mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg);  in ccu_enable_win()
144 static void ccu_disable_win(int ap_index, uint32_t win_id)  in ccu_disable_win()  argument
153 	win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));  in ccu_disable_win()
155 	mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg);  in ccu_disable_win()
166 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size)  in ccu_temp_win_insert()  argument
173 		ccu_enable_win(ap_index, win, win_id);  in ccu_temp_win_insert()
182 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size)  in ccu_temp_win_remove()  argument
192 		target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));  in ccu_temp_win_remove()
196 		base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id));  in ccu_temp_win_remove()
204 		ccu_disable_win(ap_index, win_id);  in ccu_temp_win_remove()
215 static uint32_t ccu_dram_target_get(int ap_index)  in ccu_dram_target_get()  argument
222 	const uint32_t win_id = (ap_index == 0) ? 2 : 1;  in ccu_dram_target_get()
225 	target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));  in ccu_dram_target_get()
232 void ccu_dram_target_set(int ap_index, uint32_t target)  in ccu_dram_target_set()  argument
239 	const uint32_t win_id = (ap_index == 0) ? 2 : 1;  in ccu_dram_target_set()
242 	dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));  in ccu_dram_target_set()
245 	mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr);  in ccu_dram_target_set()
249 void ccu_dram_win_config(int ap_index, struct addr_map_win *win)  in ccu_dram_win_config()  argument
256 	const uint32_t win_id = (ap_index == 0) ? 2 : 1;  in ccu_dram_win_config()
266 	ccu_disable_win(ap_index, win_id);  in ccu_dram_win_config()
268 	mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id),  in ccu_dram_win_config()
271 	ccu_enable_win(ap_index, win, win_id);  in ccu_dram_win_config()
314 int init_ccu(int ap_index)  in init_ccu()  argument
332 	marvell_get_ccu_memory_map(ap_index, &win, &win_count);  in init_ccu()
347 	dram_target = ccu_dram_target_get(ap_index);  in init_ccu()
349 	mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg);  in init_ccu()
368 		ccu_disable_win(ap_index, win_id);  in init_ccu()
370 		mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id),  in init_ccu()
381 		ccu_enable_win(ap_index, win, win_id);  in init_ccu()
387 	win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK)  in init_ccu()
389 	mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg);  in init_ccu()
392 	dump_ccu(ap_index);  in init_ccu()