Lines Matching refs:mask
109 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_pipe_selector() local
113 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_pipe_selector()
115 field = reg & mask; in mvebu_cp110_comphy_clr_pipe_selector()
118 reg &= ~mask; in mvebu_cp110_comphy_clr_pipe_selector()
128 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_phy_selector() local
132 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_phy_selector()
134 field = reg & mask; in mvebu_cp110_comphy_clr_phy_selector()
142 reg &= ~mask; in mvebu_cp110_comphy_clr_phy_selector()
152 uint32_t reg, mask; in mvebu_cp110_comphy_set_phy_selector() local
167 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_set_phy_selector()
169 reg &= ~mask; in mvebu_cp110_comphy_set_phy_selector()
249 uint32_t mask = COMMON_SELECTOR_COMPHY_MASK << shift; in mvebu_cp110_comphy_set_pipe_selector() local
258 reg &= ~mask; in mvebu_cp110_comphy_set_pipe_selector()
298 uint32_t mask, data; in mvebu_cp110_comphy_is_pll_locked() local
309 mask = data; in mvebu_cp110_comphy_is_pll_locked()
310 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_is_pll_locked()
328 uint32_t mask, data; in mvebu_cp110_polarity_invert() local
331 data = mask = 0x0U; in mvebu_cp110_polarity_invert()
334 mask |= HPIPE_SYNC_PATTERN_TXD_INV_MASK; in mvebu_cp110_polarity_invert()
340 mask |= HPIPE_SYNC_PATTERN_RXD_INV_MASK; in mvebu_cp110_polarity_invert()
344 reg_set(addr, data, mask); in mvebu_cp110_polarity_invert()
351 uint32_t mask, data; in mvebu_cp110_comphy_sata_power_on() local
378 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_sata_power_on()
380 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_sata_power_on()
382 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_sata_power_on()
384 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_sata_power_on()
386 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
394 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_sata_power_on()
396 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_sata_power_on()
398 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
410 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_sata_power_on()
413 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_sata_power_on()
415 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
426 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_sata_power_on()
429 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_sata_power_on()
432 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in mvebu_cp110_comphy_sata_power_on()
435 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in mvebu_cp110_comphy_sata_power_on()
438 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_sata_power_on()
440 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
442 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
444 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
446 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
448 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
450 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
452 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
455 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in mvebu_cp110_comphy_sata_power_on()
458 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; in mvebu_cp110_comphy_sata_power_on()
461 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in mvebu_cp110_comphy_sata_power_on()
464 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; in mvebu_cp110_comphy_sata_power_on()
467 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_sata_power_on()
469 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
472 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in mvebu_cp110_comphy_sata_power_on()
475 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in mvebu_cp110_comphy_sata_power_on()
478 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; in mvebu_cp110_comphy_sata_power_on()
481 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; in mvebu_cp110_comphy_sata_power_on()
484 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
486 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_sata_power_on()
488 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
490 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
493 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
495 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
497 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
499 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
501 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
503 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; in mvebu_cp110_comphy_sata_power_on()
505 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
507 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
510 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_sata_power_on()
512 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
513 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_sata_power_on()
515 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
518 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in mvebu_cp110_comphy_sata_power_on()
520 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
523 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
525 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_sata_power_on()
528 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
530 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in mvebu_cp110_comphy_sata_power_on()
532 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
535 mask = HPIPE_G3_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
538 mask |= HPIPE_G3_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
541 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
543 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
545 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in mvebu_cp110_comphy_sata_power_on()
547 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
550 mask = HPIPE_G3_DFE_RES_MASK; in mvebu_cp110_comphy_sata_power_on()
552 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
555 mask = HPIPE_OS_PH_OFFSET_MASK; in mvebu_cp110_comphy_sata_power_on()
557 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; in mvebu_cp110_comphy_sata_power_on()
559 mask |= HPIPE_OS_PH_VALID_MASK; in mvebu_cp110_comphy_sata_power_on()
561 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
562 mask = HPIPE_OS_PH_VALID_MASK; in mvebu_cp110_comphy_sata_power_on()
564 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
565 mask = HPIPE_OS_PH_VALID_MASK; in mvebu_cp110_comphy_sata_power_on()
567 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
570 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in mvebu_cp110_comphy_sata_power_on()
572 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_sata_power_on()
575 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in mvebu_cp110_comphy_sata_power_on()
578 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
581 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
584 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
587 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; in mvebu_cp110_comphy_sata_power_on()
590 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
593 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; in mvebu_cp110_comphy_sata_power_on()
595 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_sata_power_on()
598 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; in mvebu_cp110_comphy_sata_power_on()
601 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
604 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
607 mask = HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
610 mask |= HPIPE_G2_SET_2_G2_TX_EMPH0_MASK; in mvebu_cp110_comphy_sata_power_on()
613 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
616 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; in mvebu_cp110_comphy_sata_power_on()
618 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_sata_power_on()
621 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; in mvebu_cp110_comphy_sata_power_on()
624 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
627 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; in mvebu_cp110_comphy_sata_power_on()
629 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
631 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
634 mask = HPIPE_G3_SET_2_G3_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_sata_power_on()
637 mask |= HPIPE_G3_SET_2_G3_TX_EMPH0_MASK; in mvebu_cp110_comphy_sata_power_on()
640 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
643 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; in mvebu_cp110_comphy_sata_power_on()
645 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
676 uint32_t mask, data, sgmii_speed = COMPHY_GET_SPEED(comphy_mode); in mvebu_cp110_comphy_sgmii_power_on() local
694 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_sgmii_power_on()
696 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
698 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
701 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
703 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
704 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
720 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
722 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
724 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
726 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
729 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
731 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
733 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
735 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
738 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
740 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
742 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
750 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
752 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
757 mask = HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
759 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
761 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_sgmii_power_on()
763 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_sgmii_power_on()
765 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
767 mask = HPIPE_LOOPBACK_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
769 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
771 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
773 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
775 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
777 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
779 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
790 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_sgmii_power_on()
792 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
794 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_sgmii_power_on()
796 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
803 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
805 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
810 mask = data; in mvebu_cp110_comphy_sgmii_power_on()
811 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_sgmii_power_on()
819 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
821 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_sgmii_power_on()
823 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
835 uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode); in mvebu_cp110_comphy_xfi_power_on() local
887 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_xfi_power_on()
889 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_xfi_power_on()
891 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
896 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
898 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
901 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_xfi_power_on()
903 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in mvebu_cp110_comphy_xfi_power_on()
905 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in mvebu_cp110_comphy_xfi_power_on()
907 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_xfi_power_on()
909 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_xfi_power_on()
911 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
913 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
916 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
918 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_xfi_power_on()
920 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
922 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
924 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
926 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_xfi_power_on()
928 mask |= SD_EXTERNAL_CONFIG1_TX_IDLE_MASK; in mvebu_cp110_comphy_xfi_power_on()
930 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
939 mask = SD_EXTERNAL_CONFIG1_TX_IDLE_MASK; in mvebu_cp110_comphy_xfi_power_on()
941 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
946 mask = HPIPE_MISC_ICP_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
950 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
952 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
954 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_xfi_power_on()
956 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
958 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
960 mask = HPIPE_LOOPBACK_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
962 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
964 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
966 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
968 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
970 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
972 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
976 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; in mvebu_cp110_comphy_xfi_power_on()
978 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
980 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; in mvebu_cp110_comphy_xfi_power_on()
982 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
985 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
988 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
993 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
995 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
997 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
999 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1002 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in mvebu_cp110_comphy_xfi_power_on()
1005 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in mvebu_cp110_comphy_xfi_power_on()
1008 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in mvebu_cp110_comphy_xfi_power_on()
1012 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1015 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; in mvebu_cp110_comphy_xfi_power_on()
1019 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1021 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; in mvebu_cp110_comphy_xfi_power_on()
1024 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1027 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1029 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; in mvebu_cp110_comphy_xfi_power_on()
1031 mask |= HPIPE_TX_REG1_SLC_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1033 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1035 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; in mvebu_cp110_comphy_xfi_power_on()
1037 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1039 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1041 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; in mvebu_cp110_comphy_xfi_power_on()
1043 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1046 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1049 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_xfi_power_on()
1051 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_xfi_power_on()
1054 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_xfi_power_on()
1057 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_xfi_power_on()
1060 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in mvebu_cp110_comphy_xfi_power_on()
1063 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in mvebu_cp110_comphy_xfi_power_on()
1066 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in mvebu_cp110_comphy_xfi_power_on()
1069 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1072 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1074 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1076 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1079 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_power_on()
1081 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1083 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1087 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1089 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1091 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1093 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1095 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1098 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1101 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1103 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1106 mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1110 data, mask); in mvebu_cp110_comphy_xfi_power_on()
1113 mask = HPIPE_CAL_OS_PH_EXT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1117 data, mask); in mvebu_cp110_comphy_xfi_power_on()
1120 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1122 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1125 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_power_on()
1128 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1132 mask = HPIPE_RX_TRAIN_TIMER_MASK; in mvebu_cp110_comphy_xfi_power_on()
1134 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1137 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in mvebu_cp110_comphy_xfi_power_on()
1139 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1142 mask = HPIPE_TX_PRESET_INDEX_MASK; in mvebu_cp110_comphy_xfi_power_on()
1144 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1147 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1149 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1152 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1154 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1156 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1159 mask = HPIPE_TRAIN_PAT_NUM_MASK; in mvebu_cp110_comphy_xfi_power_on()
1161 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1164 mask = HPIPE_DME_ETHERNET_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1166 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1169 mask = HPIPE_CAL_VDD_CONT_MODE_MASK; in mvebu_cp110_comphy_xfi_power_on()
1171 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1174 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1176 mask |= HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_xfi_power_on()
1178 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1179 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_xfi_power_on()
1181 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1184 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1186 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1190 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_xfi_power_on()
1192 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_xfi_power_on()
1194 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_xfi_power_on()
1196 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1202 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1203 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_xfi_power_on()
1215 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1217 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1222 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1223 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_xfi_power_on()
1231 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1233 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_xfi_power_on()
1235 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1246 uint32_t reg, mask, data, pcie_width; in mvebu_cp110_comphy_pcie_power_on() local
1322 mask = COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1324 data, mask); in mvebu_cp110_comphy_pcie_power_on()
1327 mask = COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1328 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1339 mask = DFX_DEV_GEN_PCIE_CLK_SRC_MASK; in mvebu_cp110_comphy_pcie_power_on()
1341 DFX_DEV_GEN_CTRL12_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1346 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_pcie_power_on()
1348 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1350 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_pcie_power_on()
1352 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1354 mask |= COMMON_PHY_PHY_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1356 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1359 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_pcie_power_on()
1361 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1363 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1370 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in mvebu_cp110_comphy_pcie_power_on()
1373 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in mvebu_cp110_comphy_pcie_power_on()
1376 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in mvebu_cp110_comphy_pcie_power_on()
1379 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1381 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1384 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1387 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1389 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1391 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1395 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1397 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1398 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; in mvebu_cp110_comphy_pcie_power_on()
1399 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; in mvebu_cp110_comphy_pcie_power_on()
1407 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1410 mask = HPIPE_CFG_UPDATE_POLARITY_MASK; in mvebu_cp110_comphy_pcie_power_on()
1411 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1414 mask = HPIPE_DFE_CTRL_28_PIPE4_MASK; in mvebu_cp110_comphy_pcie_power_on()
1415 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1418 mask = 0; in mvebu_cp110_comphy_pcie_power_on()
1422 mask |= HPIPE_MISC_CLK100M_125M_MASK; in mvebu_cp110_comphy_pcie_power_on()
1426 mask |= HPIPE_MISC_TXDCLK_2X_MASK; in mvebu_cp110_comphy_pcie_power_on()
1429 mask |= HPIPE_MISC_CLK500_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1433 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1437 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1440 mask |= HPIPE_MISC_ICP_FORCE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1442 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1445 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_pcie_power_on()
1449 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_pcie_power_on()
1453 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1455 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1459 mask = HPIPE_LANE_ALIGN_OFF_MASK; in mvebu_cp110_comphy_pcie_power_on()
1461 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1473 mask = HPIPE_INTERFACE_GEN_MAX_MASK; in mvebu_cp110_comphy_pcie_power_on()
1476 mask |= HPIPE_INTERFACE_DET_BYPASS_MASK; in mvebu_cp110_comphy_pcie_power_on()
1479 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1481 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1484 mask = HPIPE_PCIE_IDLE_SYNC_MASK; in mvebu_cp110_comphy_pcie_power_on()
1487 mask |= HPIPE_PCIE_SEL_BITS_MASK; in mvebu_cp110_comphy_pcie_power_on()
1489 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1492 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1495 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1498 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; in mvebu_cp110_comphy_pcie_power_on()
1500 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1503 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1506 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; in mvebu_cp110_comphy_pcie_power_on()
1508 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1512 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1514 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; in mvebu_cp110_comphy_pcie_power_on()
1516 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1518 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1521 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1523 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1525 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1527 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1529 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1532 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in mvebu_cp110_comphy_pcie_power_on()
1534 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1537 mask = HPIPE_TRX_TRAIN_TIMER_MASK; in mvebu_cp110_comphy_pcie_power_on()
1539 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1542 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK in mvebu_cp110_comphy_pcie_power_on()
1545 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1548 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1550 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1553 mask = HPIPE_G3_DFE_RES_MASK; in mvebu_cp110_comphy_pcie_power_on()
1555 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1558 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1560 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1563 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in mvebu_cp110_comphy_pcie_power_on()
1566 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in mvebu_cp110_comphy_pcie_power_on()
1569 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1571 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1574 mask = HPIPE_SMAPLER_MASK; in mvebu_cp110_comphy_pcie_power_on()
1576 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1578 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); in mvebu_cp110_comphy_pcie_power_on()
1581 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1583 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1585 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1588 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1590 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1593 mask = HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK; in mvebu_cp110_comphy_pcie_power_on()
1595 mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1597 mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; in mvebu_cp110_comphy_pcie_power_on()
1599 mask |= HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; in mvebu_cp110_comphy_pcie_power_on()
1601 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1603 mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1605 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1608 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in mvebu_cp110_comphy_pcie_power_on()
1610 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; in mvebu_cp110_comphy_pcie_power_on()
1612 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in mvebu_cp110_comphy_pcie_power_on()
1614 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1617 mask = HPIPE_G2_DFE_RES_MASK; in mvebu_cp110_comphy_pcie_power_on()
1619 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1622 mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1624 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1627 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in mvebu_cp110_comphy_pcie_power_on()
1629 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1632 mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; in mvebu_cp110_comphy_pcie_power_on()
1634 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1637 mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1639 mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; in mvebu_cp110_comphy_pcie_power_on()
1641 mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; in mvebu_cp110_comphy_pcie_power_on()
1643 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1645 mask = HPIPE_CFG_EQ_BUNDLE_DIS_MASK; in mvebu_cp110_comphy_pcie_power_on()
1647 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1661 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1663 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1664 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1696 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1706 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK; in mvebu_cp110_comphy_pcie_power_on()
1709 data, mask); in mvebu_cp110_comphy_pcie_power_on()
1719 mask = data; in mvebu_cp110_comphy_pcie_power_on()
1720 ret = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_pcie_power_on()
1737 uint32_t mask, data; in mvebu_cp110_comphy_rxaui_power_on() local
1753 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1755 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1757 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1771 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1773 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1775 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1777 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1779 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1781 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1783 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1785 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1788 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1790 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1792 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1794 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1796 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1798 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1800 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1812 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1814 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1816 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1821 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1823 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1825 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1845 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1847 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1849 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1851 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1853 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1855 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1857 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1860 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1862 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1866 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1868 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1870 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1872 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1879 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
1880 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT); in mvebu_cp110_comphy_rxaui_power_on()
1898 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
1899 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_rxaui_power_on()
1909 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1911 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1913 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1924 uint32_t mask, data; in mvebu_cp110_comphy_usb3_power_on() local
1947 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_usb3_power_on()
1949 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_usb3_power_on()
1951 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_usb3_power_on()
1953 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_usb3_power_on()
1955 mask |= COMMON_PHY_PHY_MODE_MASK; in mvebu_cp110_comphy_usb3_power_on()
1957 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1960 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_usb3_power_on()
1962 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_usb3_power_on()
1964 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1972 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in mvebu_cp110_comphy_usb3_power_on()
1975 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in mvebu_cp110_comphy_usb3_power_on()
1978 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in mvebu_cp110_comphy_usb3_power_on()
1981 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in mvebu_cp110_comphy_usb3_power_on()
1983 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1993 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in mvebu_cp110_comphy_usb3_power_on()
1996 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in mvebu_cp110_comphy_usb3_power_on()
1998 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2030 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; in mvebu_cp110_comphy_usb3_power_on()
2033 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; in mvebu_cp110_comphy_usb3_power_on()
2036 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; in mvebu_cp110_comphy_usb3_power_on()
2038 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2040 mask = HPIPE_G2_TX_SSC_AMP_MASK; in mvebu_cp110_comphy_usb3_power_on()
2042 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2056 mask = data; in mvebu_cp110_comphy_usb3_power_on()
2057 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT); in mvebu_cp110_comphy_usb3_power_on()
2073 uint32_t mask, data; in rx_pre_train() local
2080 mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK; in rx_pre_train()
2082 mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK; in rx_pre_train()
2084 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask); in rx_pre_train()
2087 mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK; in rx_pre_train()
2089 mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK; in rx_pre_train()
2091 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask); in rx_pre_train()
2093 mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK; in rx_pre_train()
2095 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2097 mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK; in rx_pre_train()
2099 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask); in rx_pre_train()
2101 mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK; in rx_pre_train()
2103 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask); in rx_pre_train()
2105 mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK; in rx_pre_train()
2107 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in rx_pre_train()
2109 mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK; in rx_pre_train()
2111 mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK; in rx_pre_train()
2113 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2119 uint32_t mask, data, timeout; in mvebu_cp110_comphy_xfi_rx_training() local
2137 mask = HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2139 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2142 mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2145 data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2148 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2150 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2154 mask = HPIPE_TRX_RX_TRAIN_EN_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2156 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2160 mask = HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET | in mvebu_cp110_comphy_xfi_rx_training()
2165 if (data & mask) in mvebu_cp110_comphy_xfi_rx_training()
2184 mask = HPIPE_TRX_RX_TRAIN_EN_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2186 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2190 mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2193 & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2195 mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2198 & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2200 mask = HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2202 & mask) >> HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2204 mask = HPIPE_ADAPTED_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2207 & mask) >> HPIPE_ADAPTED_DFE_RES_OFFSET); in mvebu_cp110_comphy_xfi_rx_training()
2224 mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2226 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2229 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2231 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2236 mask = HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2238 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2241 mask = HPIPE_DFE_RES_FORCE_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2243 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2246 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in mvebu_cp110_comphy_xfi_rx_training()
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2286 uint32_t mask, data; in mvebu_cp110_comphy_ap_power_on() local
2297 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in mvebu_cp110_comphy_ap_power_on()
2299 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in mvebu_cp110_comphy_ap_power_on()
2301 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_ap_power_on()
2321 uint32_t mask, data; in mvebu_cp110_comphy_digital_reset() local
2332 mask = SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_digital_reset()
2335 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_digital_reset()
2408 uint32_t mask, data; in mvebu_cp110_comphy_power_off() local
2456 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in mvebu_cp110_comphy_power_off()
2458 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in mvebu_cp110_comphy_power_off()
2460 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in mvebu_cp110_comphy_power_off()
2462 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_power_off()
2490 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in mvebu_cp110_comphy_power_off()
2492 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in mvebu_cp110_comphy_power_off()
2494 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_power_off()