Lines Matching refs:reg_set
344 reg_set(addr, data, mask); in mvebu_cp110_polarity_invert()
386 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
389 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, in mvebu_cp110_comphy_sata_power_on()
398 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
406 reg_set(hpipe_addr + HPIPE_MISC_REG, in mvebu_cp110_comphy_sata_power_on()
415 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
417 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, in mvebu_cp110_comphy_sata_power_on()
421 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, in mvebu_cp110_comphy_sata_power_on()
440 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
452 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
469 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
490 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
507 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
512 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
515 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
520 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
525 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_sata_power_on()
532 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
547 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
552 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
561 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
564 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
567 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
581 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
590 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
604 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
613 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
631 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
640 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
645 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
648 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, in mvebu_cp110_comphy_sata_power_on()
651 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, in mvebu_cp110_comphy_sata_power_on()
660 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, in mvebu_cp110_comphy_sata_power_on()
663 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, in mvebu_cp110_comphy_sata_power_on()
698 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
726 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
735 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
742 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
752 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
759 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
765 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
769 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
775 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
779 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
784 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, in mvebu_cp110_comphy_sgmii_power_on()
796 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
805 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
823 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
891 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
898 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
913 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
922 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
930 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
941 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
952 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
958 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
962 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
968 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
972 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
988 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
995 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
999 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1019 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1027 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1033 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1039 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1043 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1069 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1076 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1081 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1093 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1103 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1108 reg_set(hpipe_addr + in mvebu_cp110_comphy_xfi_power_on()
1115 reg_set(hpipe_addr + in mvebu_cp110_comphy_xfi_power_on()
1122 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1128 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1134 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1139 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1144 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1149 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1156 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1161 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1166 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1171 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1178 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1181 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1186 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1196 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1217 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1235 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1323 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in mvebu_cp110_comphy_pcie_power_on()
1328 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1340 reg_set(DFX_FROM_COMPHY_ADDR(comphy_base) + in mvebu_cp110_comphy_pcie_power_on()
1356 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1363 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1381 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1391 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1407 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1411 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1415 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1442 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1455 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1461 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1468 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, in mvebu_cp110_comphy_pcie_power_on()
1481 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1489 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1500 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1508 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1518 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1529 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1534 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1539 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1545 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1550 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1555 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1560 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1571 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1576 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1578 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); in mvebu_cp110_comphy_pcie_power_on()
1585 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1590 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1601 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1605 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1614 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1619 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1624 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1629 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1634 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1643 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1647 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1664 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1673 reg_set(HPIPE_ADDR( in mvebu_cp110_comphy_pcie_power_on()
1684 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, in mvebu_cp110_comphy_pcie_power_on()
1708 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in mvebu_cp110_comphy_pcie_power_on()
1757 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1760 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in mvebu_cp110_comphy_rxaui_power_on()
1765 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in mvebu_cp110_comphy_rxaui_power_on()
1785 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1794 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1800 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1808 reg_set(hpipe_addr + HPIPE_MISC_REG, in mvebu_cp110_comphy_rxaui_power_on()
1816 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1818 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, in mvebu_cp110_comphy_rxaui_power_on()
1825 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1827 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, in mvebu_cp110_comphy_rxaui_power_on()
1834 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, in mvebu_cp110_comphy_rxaui_power_on()
1838 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, in mvebu_cp110_comphy_rxaui_power_on()
1841 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, in mvebu_cp110_comphy_rxaui_power_on()
1851 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1857 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1862 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1872 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1891 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, in mvebu_cp110_comphy_rxaui_power_on()
1913 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1957 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1964 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1983 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1985 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, in mvebu_cp110_comphy_usb3_power_on()
1989 reg_set(hpipe_addr + HPIPE_MISC_REG, in mvebu_cp110_comphy_usb3_power_on()
1998 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2000 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, in mvebu_cp110_comphy_usb3_power_on()
2004 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, in mvebu_cp110_comphy_usb3_power_on()
2008 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, in mvebu_cp110_comphy_usb3_power_on()
2012 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, in mvebu_cp110_comphy_usb3_power_on()
2016 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, in mvebu_cp110_comphy_usb3_power_on()
2038 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2042 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2047 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, in mvebu_cp110_comphy_usb3_power_on()
2084 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask); in rx_pre_train()
2091 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask); in rx_pre_train()
2095 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2099 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask); in rx_pre_train()
2103 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask); in rx_pre_train()
2107 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in rx_pre_train()
2113 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2139 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2144 reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG, in mvebu_cp110_comphy_xfi_rx_training()
2150 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2156 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2186 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2226 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2231 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2238 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2243 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2301 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_ap_power_on()
2335 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_digital_reset()
2462 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_power_off()
2494 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_power_off()