Lines Matching refs:ULL
30 #define MPIDR_MT_MASK (ULL(1) << 24)
34 #define MPIDR_AFFLVL_MASK ULL(0xff)
40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
42 #define MPIDR_AFFLVL0 ULL(0x0)
43 #define MPIDR_AFFLVL1 ULL(0x1)
44 #define MPIDR_AFFLVL2 ULL(0x2)
45 #define MPIDR_AFFLVL3 ULL(0x3)
163 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
164 #define ID_AA64PFR0_ELX_MASK ULL(0xf)
167 #define ID_AA64PFR0_GIC_MASK ULL(0xf)
169 #define ID_AA64PFR0_SVE_MASK ULL(0xf)
171 #define ID_AA64PFR0_SEL2_MASK ULL(0xf)
173 #define ID_AA64PFR0_MPAM_MASK ULL(0xf)
175 #define ID_AA64PFR0_DIT_MASK ULL(0xf)
179 #define ID_AA64PFR0_CSV2_MASK ULL(0xf)
183 #define EL_IMPL_NONE ULL(0)
184 #define EL_IMPL_A64ONLY ULL(1)
185 #define EL_IMPL_A64_A32 ULL(2)
189 #define ID_AA64DFR0_PMS_MASK ULL(0xf)
193 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
194 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
198 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
203 #define ID_AA64ISAR1_GPI_MASK ULL(0xf)
205 #define ID_AA64ISAR1_GPA_MASK ULL(0xf)
207 #define ID_AA64ISAR1_API_MASK ULL(0xf)
209 #define ID_AA64ISAR1_APA_MASK ULL(0xf)
213 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
224 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
225 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
226 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
227 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
230 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
231 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
232 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
235 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
236 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
237 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
240 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
241 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
242 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
245 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
246 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
247 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
251 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
252 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
253 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
256 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
257 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
258 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
259 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
260 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
266 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
269 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
273 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
275 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
278 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
280 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
283 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
297 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
298 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
322 #define SCTLR_M_BIT (ULL(1) << 0)
323 #define SCTLR_A_BIT (ULL(1) << 1)
324 #define SCTLR_C_BIT (ULL(1) << 2)
325 #define SCTLR_SA_BIT (ULL(1) << 3)
326 #define SCTLR_SA0_BIT (ULL(1) << 4)
327 #define SCTLR_CP15BEN_BIT (ULL(1) << 5)
328 #define SCTLR_nAA_BIT (ULL(1) << 6)
329 #define SCTLR_ITD_BIT (ULL(1) << 7)
330 #define SCTLR_SED_BIT (ULL(1) << 8)
331 #define SCTLR_UMA_BIT (ULL(1) << 9)
332 #define SCTLR_EnRCTX_BIT (ULL(1) << 10)
333 #define SCTLR_EOS_BIT (ULL(1) << 11)
334 #define SCTLR_I_BIT (ULL(1) << 12)
335 #define SCTLR_EnDB_BIT (ULL(1) << 13)
336 #define SCTLR_DZE_BIT (ULL(1) << 14)
337 #define SCTLR_UCT_BIT (ULL(1) << 15)
338 #define SCTLR_NTWI_BIT (ULL(1) << 16)
339 #define SCTLR_NTWE_BIT (ULL(1) << 18)
340 #define SCTLR_WXN_BIT (ULL(1) << 19)
341 #define SCTLR_TSCXT_BIT (ULL(1) << 20)
342 #define SCTLR_IESB_BIT (ULL(1) << 21)
343 #define SCTLR_EIS_BIT (ULL(1) << 22)
344 #define SCTLR_SPAN_BIT (ULL(1) << 23)
345 #define SCTLR_E0E_BIT (ULL(1) << 24)
346 #define SCTLR_EE_BIT (ULL(1) << 25)
347 #define SCTLR_UCI_BIT (ULL(1) << 26)
348 #define SCTLR_EnDA_BIT (ULL(1) << 27)
349 #define SCTLR_nTLSMD_BIT (ULL(1) << 28)
350 #define SCTLR_LSMAOE_BIT (ULL(1) << 29)
351 #define SCTLR_EnIB_BIT (ULL(1) << 30)
352 #define SCTLR_EnIA_BIT (ULL(1) << 31)
353 #define SCTLR_BT0_BIT (ULL(1) << 35)
354 #define SCTLR_BT1_BIT (ULL(1) << 36)
355 #define SCTLR_BT_BIT (ULL(1) << 36)
356 #define SCTLR_ITFSB_BIT (ULL(1) << 37)
358 #define SCTLR_TCF0_MASK ULL(3)
373 #define SCTLR_TCF_MASK ULL(3)
387 #define SCTLR_ATA0_BIT (ULL(1) << 42)
388 #define SCTLR_ATA_BIT (ULL(1) << 43)
389 #define SCTLR_DSSBS_BIT (ULL(1) << 44)
390 #define SCTLR_TWEDEn_BIT (ULL(1) << 45)
392 #define SCTLR_TWEDEL_MASK ULL(0xf)
393 #define SCTLR_EnASR_BIT (ULL(1) << 54)
394 #define SCTLR_EnAS0_BIT (ULL(1) << 55)
395 #define SCTLR_EnALS_BIT (ULL(1) << 56)
396 #define SCTLR_EPAN_BIT (ULL(1) << 57)
408 #define SCR_TWEDEL_MASK ULL(0xf)
433 #define MDCR_MTPME_BIT (ULL(1) << 28)
434 #define MDCR_SCCD_BIT (ULL(1) << 23)
435 #define MDCR_SPME_BIT (ULL(1) << 17)
436 #define MDCR_SDD_BIT (ULL(1) << 16)
438 #define MDCR_SPD32_LEGACY ULL(0x0)
439 #define MDCR_SPD32_DISABLE ULL(0x2)
440 #define MDCR_SPD32_ENABLE ULL(0x3)
442 #define MDCR_NSPB_EL1 ULL(0x3)
443 #define MDCR_TDOSA_BIT (ULL(1) << 10)
444 #define MDCR_TDA_BIT (ULL(1) << 9)
445 #define MDCR_TPM_BIT (ULL(1) << 6)
446 #define MDCR_EL3_RESET_VAL ULL(0x0)
475 #define VTTBR_RESET_VAL ULL(0x0)
476 #define VTTBR_VMID_MASK ULL(0xff)
478 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
482 #define HCR_API_BIT (ULL(1) << 41)
483 #define HCR_APK_BIT (ULL(1) << 40)
484 #define HCR_E2H_BIT (ULL(1) << 34)
485 #define HCR_TGE_BIT (ULL(1) << 27)
487 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
488 #define HCR_AMO_BIT (ULL(1) << 5)
489 #define HCR_IMO_BIT (ULL(1) << 4)
490 #define HCR_FMO_BIT (ULL(1) << 3)
581 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
582 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
587 #define TCR_TxSZ_MIN ULL(16)
588 #define TCR_TxSZ_MAX ULL(39)
589 #define TCR_TxSZ_MAX_TTST ULL(48)
595 #define TCR_PS_BITS_4GB ULL(0x0)
596 #define TCR_PS_BITS_64GB ULL(0x1)
597 #define TCR_PS_BITS_1TB ULL(0x2)
598 #define TCR_PS_BITS_4TB ULL(0x3)
599 #define TCR_PS_BITS_16TB ULL(0x4)
600 #define TCR_PS_BITS_256TB ULL(0x5)
602 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
603 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
604 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
605 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
606 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
607 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
609 #define TCR_RGN_INNER_NC (ULL(0x0) << 8)
610 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
611 #define TCR_RGN_INNER_WT (ULL(0x2) << 8)
612 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
614 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
615 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
616 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
617 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
619 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
620 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
621 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
623 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
624 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
625 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
626 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
628 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
629 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
630 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
631 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
633 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
634 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
635 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
638 #define TCR_TG0_MASK ULL(3)
639 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
640 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
641 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
644 #define TCR_TG1_MASK ULL(3)
645 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
646 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
647 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
649 #define TCR_EPD0_BIT (ULL(1) << 7)
650 #define TCR_EPD1_BIT (ULL(1) << 23)
705 #define TTBR_CNP_BIT ULL(0x1)
788 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
852 #define MAIR_DEV_nGnRnE ULL(0x0)
853 #define MAIR_DEV_nGnRE ULL(0x4)
854 #define MAIR_DEV_nGRE ULL(0x8)
855 #define MAIR_DEV_GRE ULL(0xc)
875 #define MAIR_NORM_WT_TR_WA ULL(0x1)
876 #define MAIR_NORM_WT_TR_RA ULL(0x2)
877 #define MAIR_NORM_WT_TR_RWA ULL(0x3)
878 #define MAIR_NORM_NC ULL(0x4)
879 #define MAIR_NORM_WB_TR_WA ULL(0x5)
880 #define MAIR_NORM_WB_TR_RA ULL(0x6)
881 #define MAIR_NORM_WB_TR_RWA ULL(0x7)
882 #define MAIR_NORM_WT_NTR_NA ULL(0x8)
883 #define MAIR_NORM_WT_NTR_WA ULL(0x9)
884 #define MAIR_NORM_WT_NTR_RA ULL(0xa)
885 #define MAIR_NORM_WT_NTR_RWA ULL(0xb)
886 #define MAIR_NORM_WB_NTR_NA ULL(0xc)
887 #define MAIR_NORM_WB_NTR_WA ULL(0xd)
888 #define MAIR_NORM_WB_NTR_RA ULL(0xe)
889 #define MAIR_NORM_WB_NTR_RWA ULL(0xf)
898 #define PAR_F_MASK ULL(0x1)
900 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
986 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
987 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
989 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
990 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
992 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)