Lines Matching refs:x9
48 mrs x9, actlr_el2
50 stp x9, x10, [x0, #CTX_ACTLR_EL2]
65 mrs x9, cptr_el2
66 stp x17, x9, [x0, #CTX_CNTVOFF_EL2]
84 mrs x9, hpfar_el2
86 stp x9, x10, [x0, #CTX_HPFAR_EL2]
105 mrs x9, spsr_el2
106 stp x17, x9, [x0, #CTX_SCTLR_EL2]
124 mrs x9, vttbr_el2
125 str x9, [x0, #CTX_VTTBR_EL2]
133 mrs x9, MPAM2_EL2
135 stp x9, x10, [x0, #CTX_MPAM2_EL2]
150 mrs x9, MPAMVPM7_EL2
151 stp x17, x9, [x0, #CTX_MPAMVPM6_EL2]
176 mrs x9, cnthps_ctl_el2
178 stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2]
193 mrs x9, contextidr_el2
194 stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2]
226 mrs x9, scxtnum_el2
227 str x9, [x0, #CTX_SCXTNUM_EL2]
250 ldp x9, x10, [x0, #CTX_ACTLR_EL2]
251 msr actlr_el2, x9
266 ldp x17, x9, [x0, #CTX_CNTVOFF_EL2]
268 msr cptr_el2, x9
286 ldp x9, x10, [x0, #CTX_HPFAR_EL2]
287 msr hpfar_el2, x9
306 ldp x17, x9, [x0, #CTX_SCTLR_EL2]
308 msr spsr_el2, x9
330 ldr x9, [x0, #CTX_TFSR_EL2]
331 msr TFSR_EL2, x9
351 ldp x9, x10, [x0, #CTX_MPAMVPM6_EL2]
352 msr MPAMVPM6_EL2, x9
372 ldr x9, [x0, #CTX_CNTPOFF_EL2]
373 msr CNTPOFF_EL2, x9
393 ldp x9, x10, [x0, #CTX_CNTHV_TVAL_EL2]
394 msr cnthv_tval_el2, x9
422 ldr x9, [x0, #CTX_TRFCR_EL2]
423 msr TRFCR_EL2, x9
445 mrs x9, spsr_el1
447 stp x9, x10, [x0, #CTX_SPSR_EL1]
456 mrs x9, csselr_el1
457 stp x17, x9, [x0, #CTX_CPACR_EL1]
475 mrs x9, tpidr_el0
477 stp x9, x10, [x0, #CTX_TPIDR_EL0]
488 mrs x9, vbar_el1
489 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
526 mrs x9, RGSR_EL1
528 stp x9, x10, [x0, #CTX_RGSR_EL1]
544 ldp x9, x10, [x0, #CTX_SPSR_EL1]
545 msr spsr_el1, x9
554 ldp x17, x9, [x0, #CTX_CPACR_EL1]
556 msr csselr_el1, x9
574 ldp x9, x10, [x0, #CTX_TPIDR_EL0]
575 msr tpidr_el0, x9
586 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
588 msr vbar_el1, x9
665 mrs x9, fpsr
666 str x9, [x0, #CTX_FP_FPSR]
710 ldr x9, [x0, #CTX_FP_FPSR]
711 msr fpsr, x9
751 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
771 mrs x9, mdcr_el3
772 tst x9, #MDCR_SCCD_BIT
776 mrs x9, pmcr_el0
784 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
787 2: orr x9, x9, #PMCR_EL0_DP_BIT
788 msr pmcr_el0, x9
835 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */
846 msr APGAKeyHi_EL1, x9
876 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]