Lines Matching refs:MCUCFG_REG
16 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) macro
18 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
19 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
21 #define MP2_CPUCFG MCUCFG_REG(0x2208)
26 #define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
27 #define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
28 #define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
53 (MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
55 #define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
56 #define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
57 #define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38)
58 #define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C)
60 #define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30)
61 #define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34)
62 #define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38)
63 #define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C)
86 #define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714)
87 #define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804)
88 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
89 #define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818)
90 #define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c)
91 #define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824)
92 #define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828)
93 #define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8)
94 #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac)
95 #define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00)
96 #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04)
97 #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08)
98 #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c)
99 #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10)
100 #define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14)
101 #define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20)
102 #define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70)
103 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74)
105 #define SPARK2LDO MCUCFG_REG(0x2700)
107 #define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000)
108 #define MP0_AXI_CONFIG MCUCFG_REG(0x02C)
109 #define MP0_MISC_CONFIG0 MCUCFG_REG(0x030)
110 #define MP0_MISC_CONFIG1 MCUCFG_REG(0x034)
111 #define MP0_MISC_CONFIG2 MCUCFG_REG(0x038)
113 #define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C)
114 #define MP0_MISC_CONFIG9 MCUCFG_REG(0x054)
115 #define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064)
117 #define MP0_RW_RSVD0 MCUCFG_REG(0x06C)
120 #define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200)
121 #define MP1_AXI_CONFIG MCUCFG_REG(0x22C)
122 #define MP1_MISC_CONFIG0 MCUCFG_REG(0x230)
123 #define MP1_MISC_CONFIG1 MCUCFG_REG(0x234)
124 #define MP1_MISC_CONFIG2 MCUCFG_REG(0x238)
126 #define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C)
127 #define MP1_MISC_CONFIG9 MCUCFG_REG(0x254)
128 #define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264)
130 #define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740)
131 #define SYNC_DCM_CONFIG MCUCFG_REG(0x744)
133 #define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0)
135 #define MP0_SPMC MCUCFG_REG(0x788)
136 #define MP1_SPMC MCUCFG_REG(0x78C)
137 #define MP2_AXI_CONFIG MCUCFG_REG(0x220C)
156 #define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00)
157 #define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04)
158 #define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08)
159 #define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00)
160 #define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04)
161 #define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08)
163 #define MP2_PWR_RST_CTL MCUCFG_REG(0x2008)
164 #define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0)
165 #define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4)
167 #define MP2_COQ MCUCFG_REG(0x22BC)
170 #define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400)
171 #define MP2_CA15M_MON_L MCUCFG_REG(0x2404)
173 #define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430)
174 #define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438)
175 #define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434)
176 #define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C)
178 #define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068)
179 #define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268)
180 #define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C)