Lines Matching refs:crd
106 { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
109 { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */
253 { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */
256 { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */
259 { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */
262 { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */
265 { /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 $cop, $crd, $addr */
268 { /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $option */
271 { /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $offset */
274 { /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 $cop, $crd, $addr! */
277 { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */
280 { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */
283 { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */
286 { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */
289 { /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */
292 { /* ARM_LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */
295 { /* ARM_LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */
298 { /* ARM_LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */
886 { /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l $cop, $crd, $addr */
889 { /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $option */
892 { /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $offset */
895 { /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l $cop, $crd, $addr! */
898 { /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 $cop, $crd, $addr */
901 { /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 $cop, $crd, $addr, $option */
904 { /* ARM_STC2_POST, ARM_INS_STC2: stc2 $cop, $crd, $addr, $offset */
907 { /* ARM_STC2_PRE, ARM_INS_STC2: stc2 $cop, $crd, $addr! */
910 { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */
913 { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */
916 { /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */
919 { /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */
922 { /* ARM_STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */
925 { /* ARM_STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */
928 { /* ARM_STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */
931 { /* ARM_STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */
5392 { /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
5395 { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */
5509 { /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr */
5512 { /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $option */
5515 { /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $offset */
5518 { /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr! */
5521 { /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr */
5524 { /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $option */
5527 { /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $offset */
5530 { /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr! */
5533 { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */
5536 { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */
5539 { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */
5542 { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */
5545 { /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */
5548 { /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */
5551 { /* ARM_t2LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */
5554 { /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */
6100 { /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr */
6103 { /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $option */
6106 { /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $offset */
6109 { /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr! */
6112 { /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2${p} $cop, $crd, $addr */
6115 { /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $option */
6118 { /* ARM_t2STC2_POST, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $offset */
6121 { /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2${p} $cop, $crd, $addr! */
6124 { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */
6127 { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */
6130 { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */
6133 { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */
6136 { /* ARM_t2STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */
6139 { /* ARM_t2STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */
6142 { /* ARM_t2STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */
6145 { /* ARM_t2STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */