Lines Matching refs:Vd
1297 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); in DecodeSPRRegListOperand() local
1301 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1302 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1307 if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1310 if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1322 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); in DecodeDPRRegListOperand() local
1326 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1327 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1333 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1337 if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
5090 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); in DecodeVCVTD() local
5091 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); in DecodeVCVTD()
5107 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeVCVTD()
5121 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); in DecodeVCVTQ() local
5122 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); in DecodeVCVTQ()
5138 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeVCVTQ()