Lines Matching refs:vd

31 {	/* ARM_AESD, ARM_INS_AESD: aesd.8	$vd, $vm */
34 {	/* ARM_AESE, ARM_INS_AESE: aese.8	$vd, $vm */
37 {	/* ARM_AESIMC, ARM_INS_AESIMC: aesimc.8	$vd, $vm */
40 {	/* ARM_AESMC, ARM_INS_AESMC: aesmc.8	$vd, $vm */
688 {	/* ARM_SHA1C, ARM_INS_SHA1C: sha1c.32	$vd, $vn, $vm */
691 {	/* ARM_SHA1H, ARM_INS_SHA1H: sha1h.32	$vd, $vm */
694 {	/* ARM_SHA1M, ARM_INS_SHA1M: sha1m.32	$vd, $vn, $vm */
697 {	/* ARM_SHA1P, ARM_INS_SHA1P: sha1p.32	$vd, $vn, $vm */
700 {	/* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0.32	$vd, $vn, $vm */
703 {	/* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1.32	$vd, $vm */
706 {	/* ARM_SHA256H, ARM_INS_SHA256H: sha256h.32	$vd, $vn, $vm */
709 {	/* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2.32	$vd, $vn, $vm */
712 {	/* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0.32	$vd, $vm */
715 {	/* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1.32	$vd, $vn, $vm */
1234 {	/* ARM_VABALsv2i64, ARM_INS_VABAL: vabal${p}.s32	$vd, $vn, $vm */
1237 {	/* ARM_VABALsv4i32, ARM_INS_VABAL: vabal${p}.s16	$vd, $vn, $vm */
1240 {	/* ARM_VABALsv8i16, ARM_INS_VABAL: vabal${p}.s8	$vd, $vn, $vm */
1243 {	/* ARM_VABALuv2i64, ARM_INS_VABAL: vabal${p}.u32	$vd, $vn, $vm */
1246 {	/* ARM_VABALuv4i32, ARM_INS_VABAL: vabal${p}.u16	$vd, $vn, $vm */
1249 {	/* ARM_VABALuv8i16, ARM_INS_VABAL: vabal${p}.u8	$vd, $vn, $vm */
1252 {	/* ARM_VABAsv16i8, ARM_INS_VABA: vaba${p}.s8	$vd, $vn, $vm */
1255 {	/* ARM_VABAsv2i32, ARM_INS_VABA: vaba${p}.s32	$vd, $vn, $vm */
1258 {	/* ARM_VABAsv4i16, ARM_INS_VABA: vaba${p}.s16	$vd, $vn, $vm */
1261 {	/* ARM_VABAsv4i32, ARM_INS_VABA: vaba${p}.s32	$vd, $vn, $vm */
1264 {	/* ARM_VABAsv8i16, ARM_INS_VABA: vaba${p}.s16	$vd, $vn, $vm */
1267 {	/* ARM_VABAsv8i8, ARM_INS_VABA: vaba${p}.s8	$vd, $vn, $vm */
1270 {	/* ARM_VABAuv16i8, ARM_INS_VABA: vaba${p}.u8	$vd, $vn, $vm */
1273 {	/* ARM_VABAuv2i32, ARM_INS_VABA: vaba${p}.u32	$vd, $vn, $vm */
1276 {	/* ARM_VABAuv4i16, ARM_INS_VABA: vaba${p}.u16	$vd, $vn, $vm */
1279 {	/* ARM_VABAuv4i32, ARM_INS_VABA: vaba${p}.u32	$vd, $vn, $vm */
1282 {	/* ARM_VABAuv8i16, ARM_INS_VABA: vaba${p}.u16	$vd, $vn, $vm */
1285 {	/* ARM_VABAuv8i8, ARM_INS_VABA: vaba${p}.u8	$vd, $vn, $vm */
1288 {	/* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl${p}.s32	$vd, $vn, $vm */
1291 {	/* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl${p}.s16	$vd, $vn, $vm */
1294 {	/* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl${p}.s8	$vd, $vn, $vm */
1297 {	/* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl${p}.u32	$vd, $vn, $vm */
1300 {	/* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl${p}.u16	$vd, $vn, $vm */
1303 {	/* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl${p}.u8	$vd, $vn, $vm */
1306 {	/* ARM_VABDfd, ARM_INS_VABD: vabd${p}.f32	$vd, $vn, $vm */
1309 {	/* ARM_VABDfq, ARM_INS_VABD: vabd${p}.f32	$vd, $vn, $vm */
1312 {	/* ARM_VABDsv16i8, ARM_INS_VABD: vabd${p}.s8	$vd, $vn, $vm */
1315 {	/* ARM_VABDsv2i32, ARM_INS_VABD: vabd${p}.s32	$vd, $vn, $vm */
1318 {	/* ARM_VABDsv4i16, ARM_INS_VABD: vabd${p}.s16	$vd, $vn, $vm */
1321 {	/* ARM_VABDsv4i32, ARM_INS_VABD: vabd${p}.s32	$vd, $vn, $vm */
1324 {	/* ARM_VABDsv8i16, ARM_INS_VABD: vabd${p}.s16	$vd, $vn, $vm */
1327 {	/* ARM_VABDsv8i8, ARM_INS_VABD: vabd${p}.s8	$vd, $vn, $vm */
1330 {	/* ARM_VABDuv16i8, ARM_INS_VABD: vabd${p}.u8	$vd, $vn, $vm */
1333 {	/* ARM_VABDuv2i32, ARM_INS_VABD: vabd${p}.u32	$vd, $vn, $vm */
1336 {	/* ARM_VABDuv4i16, ARM_INS_VABD: vabd${p}.u16	$vd, $vn, $vm */
1339 {	/* ARM_VABDuv4i32, ARM_INS_VABD: vabd${p}.u32	$vd, $vn, $vm */
1342 {	/* ARM_VABDuv8i16, ARM_INS_VABD: vabd${p}.u16	$vd, $vn, $vm */
1345 {	/* ARM_VABDuv8i8, ARM_INS_VABD: vabd${p}.u8	$vd, $vn, $vm */
1354 {	/* ARM_VABSfd, ARM_INS_VABS: vabs${p}.f32	$vd, $vm */
1357 {	/* ARM_VABSfq, ARM_INS_VABS: vabs${p}.f32	$vd, $vm */
1360 {	/* ARM_VABSv16i8, ARM_INS_VABS: vabs${p}.s8	$vd, $vm */
1363 {	/* ARM_VABSv2i32, ARM_INS_VABS: vabs${p}.s32	$vd, $vm */
1366 {	/* ARM_VABSv4i16, ARM_INS_VABS: vabs${p}.s16	$vd, $vm */
1369 {	/* ARM_VABSv4i32, ARM_INS_VABS: vabs${p}.s32	$vd, $vm */
1372 {	/* ARM_VABSv8i16, ARM_INS_VABS: vabs${p}.s16	$vd, $vm */
1375 {	/* ARM_VABSv8i8, ARM_INS_VABS: vabs${p}.s8	$vd, $vm */
1378 {	/* ARM_VACGEd, ARM_INS_VACGE: vacge${p}.f32	$vd, $vn, $vm */
1381 {	/* ARM_VACGEq, ARM_INS_VACGE: vacge${p}.f32	$vd, $vn, $vm */
1384 {	/* ARM_VACGTd, ARM_INS_VACGT: vacgt${p}.f32	$vd, $vn, $vm */
1387 {	/* ARM_VACGTq, ARM_INS_VACGT: vacgt${p}.f32	$vd, $vn, $vm */
1393 {	/* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64	$vd, $vn, $vm */
1396 {	/* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32	$vd, $vn, $vm */
1399 {	/* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16	$vd, $vn, $vm */
1402 {	/* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl${p}.s32	$vd, $vn, $vm */
1405 {	/* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl${p}.s16	$vd, $vn, $vm */
1408 {	/* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl${p}.s8	$vd, $vn, $vm */
1411 {	/* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl${p}.u32	$vd, $vn, $vm */
1414 {	/* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl${p}.u16	$vd, $vn, $vm */
1417 {	/* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl${p}.u8	$vd, $vn, $vm */
1423 {	/* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw${p}.s32	$vd, $vn, $vm */
1426 {	/* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw${p}.s16	$vd, $vn, $vm */
1429 {	/* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw${p}.s8	$vd, $vn, $vm */
1432 {	/* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw${p}.u32	$vd, $vn, $vm */
1435 {	/* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw${p}.u16	$vd, $vn, $vm */
1438 {	/* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw${p}.u8	$vd, $vn, $vm */
1441 {	/* ARM_VADDfd, ARM_INS_VADD: vadd${p}.f32	$vd, $vn, $vm */
1444 {	/* ARM_VADDfq, ARM_INS_VADD: vadd${p}.f32	$vd, $vn, $vm */
1447 {	/* ARM_VADDv16i8, ARM_INS_VADD: vadd${p}.i8	$vd, $vn, $vm */
1450 {	/* ARM_VADDv1i64, ARM_INS_VADD: vadd${p}.i64	$vd, $vn, $vm */
1453 {	/* ARM_VADDv2i32, ARM_INS_VADD: vadd${p}.i32	$vd, $vn, $vm */
1456 {	/* ARM_VADDv2i64, ARM_INS_VADD: vadd${p}.i64	$vd, $vn, $vm */
1459 {	/* ARM_VADDv4i16, ARM_INS_VADD: vadd${p}.i16	$vd, $vn, $vm */
1462 {	/* ARM_VADDv4i32, ARM_INS_VADD: vadd${p}.i32	$vd, $vn, $vm */
1465 {	/* ARM_VADDv8i16, ARM_INS_VADD: vadd${p}.i16	$vd, $vn, $vm */
1468 {	/* ARM_VADDv8i8, ARM_INS_VADD: vadd${p}.i8	$vd, $vn, $vm */
1471 {	/* ARM_VANDd, ARM_INS_VAND: vand${p}	$vd, $vn, $vm */
1474 {	/* ARM_VANDq, ARM_INS_VAND: vand${p}	$vd, $vn, $vm */
1477 {	/* ARM_VBICd, ARM_INS_VBIC: vbic${p}	$vd, $vn, $vm */
1480 {	/* ARM_VBICiv2i32, ARM_INS_VBIC: vbic${p}.i32	$vd, $simm */
1483 {	/* ARM_VBICiv4i16, ARM_INS_VBIC: vbic${p}.i16	$vd, $simm */
1486 {	/* ARM_VBICiv4i32, ARM_INS_VBIC: vbic${p}.i32	$vd, $simm */
1489 {	/* ARM_VBICiv8i16, ARM_INS_VBIC: vbic${p}.i16	$vd, $simm */
1492 {	/* ARM_VBICq, ARM_INS_VBIC: vbic${p}	$vd, $vn, $vm */
1495 {	/* ARM_VBIFd, ARM_INS_VBIF: vbif${p}	$vd, $vn, $vm */
1498 {	/* ARM_VBIFq, ARM_INS_VBIF: vbif${p}	$vd, $vn, $vm */
1501 {	/* ARM_VBITd, ARM_INS_VBIT: vbit${p}	$vd, $vn, $vm */
1504 {	/* ARM_VBITq, ARM_INS_VBIT: vbit${p}	$vd, $vn, $vm */
1507 {	/* ARM_VBSLd, ARM_INS_VBSL: vbsl${p}	$vd, $vn, $vm */
1510 {	/* ARM_VBSLq, ARM_INS_VBSL: vbsl${p}	$vd, $vn, $vm */
1513 {	/* ARM_VCEQfd, ARM_INS_VCEQ: vceq${p}.f32	$vd, $vn, $vm */
1516 {	/* ARM_VCEQfq, ARM_INS_VCEQ: vceq${p}.f32	$vd, $vn, $vm */
1519 {	/* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq${p}.i8	$vd, $vn, $vm */
1522 {	/* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq${p}.i32	$vd, $vn, $vm */
1525 {	/* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq${p}.i16	$vd, $vn, $vm */
1528 {	/* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq${p}.i32	$vd, $vn, $vm */
1531 {	/* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq${p}.i16	$vd, $vn, $vm */
1534 {	/* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq${p}.i8	$vd, $vn, $vm */
1537 {	/* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq${p}.i8	$vd, $vm, #0 */
1540 {	/* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq${p}.f32	$vd, $vm, #0 */
1543 {	/* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq${p}.i32	$vd, $vm, #0 */
1546 {	/* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq${p}.f32	$vd, $vm, #0 */
1549 {	/* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq${p}.i16	$vd, $vm, #0 */
1552 {	/* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq${p}.i32	$vd, $vm, #0 */
1555 {	/* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq${p}.i16	$vd, $vm, #0 */
1558 {	/* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq${p}.i8	$vd, $vm, #0 */
1561 {	/* ARM_VCGEfd, ARM_INS_VCGE: vcge${p}.f32	$vd, $vn, $vm */
1564 {	/* ARM_VCGEfq, ARM_INS_VCGE: vcge${p}.f32	$vd, $vn, $vm */
1567 {	/* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge${p}.s8	$vd, $vn, $vm */
1570 {	/* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge${p}.s32	$vd, $vn, $vm */
1573 {	/* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge${p}.s16	$vd, $vn, $vm */
1576 {	/* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge${p}.s32	$vd, $vn, $vm */
1579 {	/* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge${p}.s16	$vd, $vn, $vm */
1582 {	/* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge${p}.s8	$vd, $vn, $vm */
1585 {	/* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge${p}.u8	$vd, $vn, $vm */
1588 {	/* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge${p}.u32	$vd, $vn, $vm */
1591 {	/* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge${p}.u16	$vd, $vn, $vm */
1594 {	/* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge${p}.u32	$vd, $vn, $vm */
1597 {	/* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge${p}.u16	$vd, $vn, $vm */
1600 {	/* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge${p}.u8	$vd, $vn, $vm */
1603 {	/* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge${p}.s8	$vd, $vm, #0 */
1606 {	/* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge${p}.f32	$vd, $vm, #0 */
1609 {	/* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge${p}.s32	$vd, $vm, #0 */
1612 {	/* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge${p}.f32	$vd, $vm, #0 */
1615 {	/* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge${p}.s16	$vd, $vm, #0 */
1618 {	/* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge${p}.s32	$vd, $vm, #0 */
1621 {	/* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge${p}.s16	$vd, $vm, #0 */
1624 {	/* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge${p}.s8	$vd, $vm, #0 */
1627 {	/* ARM_VCGTfd, ARM_INS_VCGT: vcgt${p}.f32	$vd, $vn, $vm */
1630 {	/* ARM_VCGTfq, ARM_INS_VCGT: vcgt${p}.f32	$vd, $vn, $vm */
1633 {	/* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt${p}.s8	$vd, $vn, $vm */
1636 {	/* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt${p}.s32	$vd, $vn, $vm */
1639 {	/* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt${p}.s16	$vd, $vn, $vm */
1642 {	/* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt${p}.s32	$vd, $vn, $vm */
1645 {	/* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt${p}.s16	$vd, $vn, $vm */
1648 {	/* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt${p}.s8	$vd, $vn, $vm */
1651 {	/* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt${p}.u8	$vd, $vn, $vm */
1654 {	/* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt${p}.u32	$vd, $vn, $vm */
1657 {	/* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt${p}.u16	$vd, $vn, $vm */
1660 {	/* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt${p}.u32	$vd, $vn, $vm */
1663 {	/* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt${p}.u16	$vd, $vn, $vm */
1666 {	/* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt${p}.u8	$vd, $vn, $vm */
1669 {	/* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt${p}.s8	$vd, $vm, #0 */
1672 {	/* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt${p}.f32	$vd, $vm, #0 */
1675 {	/* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt${p}.s32	$vd, $vm, #0 */
1678 {	/* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt${p}.f32	$vd, $vm, #0 */
1681 {	/* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt${p}.s16	$vd, $vm, #0 */
1684 {	/* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt${p}.s32	$vd, $vm, #0 */
1687 {	/* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt${p}.s16	$vd, $vm, #0 */
1690 {	/* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt${p}.s8	$vd, $vm, #0 */
1693 {	/* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle${p}.s8	$vd, $vm, #0 */
1696 {	/* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle${p}.f32	$vd, $vm, #0 */
1699 {	/* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle${p}.s32	$vd, $vm, #0 */
1702 {	/* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle${p}.f32	$vd, $vm, #0 */
1705 {	/* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle${p}.s16	$vd, $vm, #0 */
1708 {	/* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle${p}.s32	$vd, $vm, #0 */
1711 {	/* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle${p}.s16	$vd, $vm, #0 */
1714 {	/* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle${p}.s8	$vd, $vm, #0 */
1717 {	/* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8	$vd, $vm */
1720 {	/* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32	$vd, $vm */
1723 {	/* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16	$vd, $vm */
1726 {	/* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32	$vd, $vm */
1729 {	/* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16	$vd, $vm */
1732 {	/* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8	$vd, $vm */
1735 {	/* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt${p}.s8	$vd, $vm, #0 */
1738 {	/* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt${p}.f32	$vd, $vm, #0 */
1741 {	/* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt${p}.s32	$vd, $vm, #0 */
1744 {	/* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt${p}.f32	$vd, $vm, #0 */
1747 {	/* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt${p}.s16	$vd, $vm, #0 */
1750 {	/* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt${p}.s32	$vd, $vm, #0 */
1753 {	/* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt${p}.s16	$vd, $vm, #0 */
1756 {	/* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt${p}.s8	$vd, $vm, #0 */
1759 {	/* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz${p}.i8	$vd, $vm */
1762 {	/* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz${p}.i32	$vd, $vm */
1765 {	/* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz${p}.i16	$vd, $vm */
1768 {	/* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz${p}.i32	$vd, $vm */
1771 {	/* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz${p}.i16	$vd, $vm */
1774 {	/* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz${p}.i8	$vd, $vm */
1801 {	/* ARM_VCNTd, ARM_INS_VCNT: vcnt${p}.8	$vd, $vm */
1804 {	/* ARM_VCNTq, ARM_INS_VCNT: vcnt${p}.8	$vd, $vm */
1807 {	/* ARM_VCVTANSD, ARM_INS_VCVTA: vcvta.s32.f32	$vd, $vm */
1810 {	/* ARM_VCVTANSQ, ARM_INS_VCVTA: vcvta.s32.f32	$vd, $vm */
1813 {	/* ARM_VCVTANUD, ARM_INS_VCVTA: vcvta.u32.f32	$vd, $vm */
1816 {	/* ARM_VCVTANUQ, ARM_INS_VCVTA: vcvta.u32.f32	$vd, $vm */
1846 {	/* ARM_VCVTMNSD, ARM_INS_VCVTM: vcvtm.s32.f32	$vd, $vm */
1849 {	/* ARM_VCVTMNSQ, ARM_INS_VCVTM: vcvtm.s32.f32	$vd, $vm */
1852 {	/* ARM_VCVTMNUD, ARM_INS_VCVTM: vcvtm.u32.f32	$vd, $vm */
1855 {	/* ARM_VCVTMNUQ, ARM_INS_VCVTM: vcvtm.u32.f32	$vd, $vm */
1870 {	/* ARM_VCVTNNSD, ARM_INS_VCVTN: vcvtn.s32.f32	$vd, $vm */
1873 {	/* ARM_VCVTNNSQ, ARM_INS_VCVTN: vcvtn.s32.f32	$vd, $vm */
1876 {	/* ARM_VCVTNNUD, ARM_INS_VCVTN: vcvtn.u32.f32	$vd, $vm */
1879 {	/* ARM_VCVTNNUQ, ARM_INS_VCVTN: vcvtn.u32.f32	$vd, $vm */
1894 {	/* ARM_VCVTPNSD, ARM_INS_VCVTP: vcvtp.s32.f32	$vd, $vm */
1897 {	/* ARM_VCVTPNSQ, ARM_INS_VCVTP: vcvtp.s32.f32	$vd, $vm */
1900 {	/* ARM_VCVTPNUD, ARM_INS_VCVTP: vcvtp.u32.f32	$vd, $vm */
1903 {	/* ARM_VCVTPNUQ, ARM_INS_VCVTP: vcvtp.u32.f32	$vd, $vm */
1933 {	/* ARM_VCVTf2h, ARM_INS_VCVT: vcvt${p}.f16.f32	$vd, $vm */
1936 {	/* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt${p}.s32.f32	$vd, $vm */
1939 {	/* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt${p}.s32.f32	$vd, $vm */
1942 {	/* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt${p}.u32.f32	$vd, $vm */
1945 {	/* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt${p}.u32.f32	$vd, $vm */
1948 {	/* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt${p}.s32.f32	$vd, $vm, $simm */
1951 {	/* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt${p}.s32.f32	$vd, $vm, $simm */
1954 {	/* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt${p}.u32.f32	$vd, $vm, $simm */
1957 {	/* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt${p}.u32.f32	$vd, $vm, $simm */
1960 {	/* ARM_VCVTh2f, ARM_INS_VCVT: vcvt${p}.f32.f16	$vd, $vm */
1963 {	/* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32	$vd, $vm */
1966 {	/* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32	$vd, $vm */
1969 {	/* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32	$vd, $vm */
1972 {	/* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32	$vd, $vm */
1975 {	/* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32	$vd, $vm, $simm */
1978 {	/* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32	$vd, $vm, $simm */
1981 {	/* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32	$vd, $vm, $simm */
1984 {	/* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32	$vd, $vm, $simm */
2011 {	/* ARM_VDUPLN16d, ARM_INS_VDUP: vdup${p}.16	$vd, $vm$lane */
2014 {	/* ARM_VDUPLN16q, ARM_INS_VDUP: vdup${p}.16	$vd, $vm$lane */
2017 {	/* ARM_VDUPLN32d, ARM_INS_VDUP: vdup${p}.32	$vd, $vm$lane */
2020 {	/* ARM_VDUPLN32q, ARM_INS_VDUP: vdup${p}.32	$vd, $vm$lane */
2023 {	/* ARM_VDUPLN8d, ARM_INS_VDUP: vdup${p}.8	$vd, $vm$lane */
2026 {	/* ARM_VDUPLN8q, ARM_INS_VDUP: vdup${p}.8	$vd, $vm$lane */
2029 {	/* ARM_VEORd, ARM_INS_VEOR: veor${p}	$vd, $vn, $vm */
2032 {	/* ARM_VEORq, ARM_INS_VEOR: veor${p}	$vd, $vn, $vm */
2035 {	/* ARM_VEXTd16, ARM_INS_VEXT: vext${p}.16	$vd, $vn, $vm, $index */
2038 {	/* ARM_VEXTd32, ARM_INS_VEXT: vext${p}.32	$vd, $vn, $vm, $index */
2041 {	/* ARM_VEXTd8, ARM_INS_VEXT: vext${p}.8	$vd, $vn, $vm, $index */
2044 {	/* ARM_VEXTq16, ARM_INS_VEXT: vext${p}.16	$vd, $vn, $vm, $index */
2047 {	/* ARM_VEXTq32, ARM_INS_VEXT: vext${p}.32	$vd, $vn, $vm, $index */
2050 {	/* ARM_VEXTq64, ARM_INS_VEXT: vext${p}.64	$vd, $vn, $vm, $index */
2053 {	/* ARM_VEXTq8, ARM_INS_VEXT: vext${p}.8	$vd, $vn, $vm, $index */
2062 {	/* ARM_VFMAfd, ARM_INS_VFMA: vfma${p}.f32	$vd, $vn, $vm */
2065 {	/* ARM_VFMAfq, ARM_INS_VFMA: vfma${p}.f32	$vd, $vn, $vm */
2074 {	/* ARM_VFMSfd, ARM_INS_VFMS: vfms${p}.f32	$vd, $vn, $vm */
2077 {	/* ARM_VFMSfq, ARM_INS_VFMS: vfms${p}.f32	$vd, $vn, $vm */
2107 {	/* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd${p}.s8	$vd, $vn, $vm */
2110 {	/* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd${p}.s32	$vd, $vn, $vm */
2113 {	/* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd${p}.s16	$vd, $vn, $vm */
2116 {	/* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd${p}.s32	$vd, $vn, $vm */
2119 {	/* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd${p}.s16	$vd, $vn, $vm */
2122 {	/* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd${p}.s8	$vd, $vn, $vm */
2125 {	/* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd${p}.u8	$vd, $vn, $vm */
2128 {	/* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd${p}.u32	$vd, $vn, $vm */
2131 {	/* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd${p}.u16	$vd, $vn, $vm */
2134 {	/* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd${p}.u32	$vd, $vn, $vm */
2137 {	/* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd${p}.u16	$vd, $vn, $vm */
2140 {	/* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd${p}.u8	$vd, $vn, $vm */
2143 {	/* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub${p}.s8	$vd, $vn, $vm */
2146 {	/* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub${p}.s32	$vd, $vn, $vm */
2149 {	/* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub${p}.s16	$vd, $vn, $vm */
2152 {	/* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub${p}.s32	$vd, $vn, $vm */
2155 {	/* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub${p}.s16	$vd, $vn, $vm */
2158 {	/* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub${p}.s8	$vd, $vn, $vm */
2161 {	/* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub${p}.u8	$vd, $vn, $vm */
2164 {	/* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub${p}.u32	$vd, $vn, $vm */
2167 {	/* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub${p}.u16	$vd, $vn, $vm */
2170 {	/* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub${p}.u32	$vd, $vn, $vm */
2173 {	/* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub${p}.u16	$vd, $vn, $vm */
2176 {	/* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub${p}.u8	$vd, $vn, $vm */
2179 {	/* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1${p}.16	$vd, $rn */
2182 {	/* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1${p}.16	$vd, $rn! */
2185 {	/* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1${p}.16	$vd, $rn, $rm */
2188 {	/* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1${p}.32	$vd, $rn */
2191 {	/* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1${p}.32	$vd, $rn! */
2194 {	/* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1${p}.32	$vd, $rn, $rm */
2197 {	/* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1${p}.8	$vd, $rn */
2200 {	/* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1${p}.8	$vd, $rn! */
2203 {	/* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1${p}.8	$vd, $rn, $rm */
2206 {	/* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1${p}.16	$vd, $rn */
2209 {	/* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1${p}.16	$vd, $rn! */
2212 {	/* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1${p}.16	$vd, $rn, $rm */
2215 {	/* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1${p}.32	$vd, $rn */
2218 {	/* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1${p}.32	$vd, $rn! */
2221 {	/* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1${p}.32	$vd, $rn, $rm */
2224 {	/* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1${p}.8	$vd, $rn */
2227 {	/* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1${p}.8	$vd, $rn! */
2230 {	/* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1${p}.8	$vd, $rn, $rm */
2233 {	/* ARM_VLD1LNd16, ARM_INS_VLD1: vld1${p}.16	\{$vd[$lane]\}, $rn */
2236 {	/* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1${p}.16	\{$vd[$lane]\}, $rn$rm */
2239 {	/* ARM_VLD1LNd32, ARM_INS_VLD1: vld1${p}.32	\{$vd[$lane]\}, $rn */
2242 {	/* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1${p}.32	\{$vd[$lane]\}, $rn$rm */
2245 {	/* ARM_VLD1LNd8, ARM_INS_VLD1: vld1${p}.8	\{$vd[$lane]\}, $rn */
2248 {	/* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1${p}.8	\{$vd[$lane]\}, $rn$rm */
2251 {	/* ARM_VLD1d16, ARM_INS_VLD1: vld1${p}.16	$vd, $rn */
2254 {	/* ARM_VLD1d16Q, ARM_INS_VLD1: vld1${p}.16	$vd, $rn */
2257 {	/* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1${p}.16	$vd, $rn! */
2260 {	/* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1${p}.16	$vd, $rn, $rm */
2263 {	/* ARM_VLD1d16T, ARM_INS_VLD1: vld1${p}.16	$vd, $rn */
2266 {	/* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1${p}.16	$vd, $rn! */
2269 {	/* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1${p}.16	$vd, $rn, $rm */
2272 {	/* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1${p}.16	$vd, $rn! */
2275 {	/* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1${p}.16	$vd, $rn, $rm */
2278 {	/* ARM_VLD1d32, ARM_INS_VLD1: vld1${p}.32	$vd, $rn */
2281 {	/* ARM_VLD1d32Q, ARM_INS_VLD1: vld1${p}.32	$vd, $rn */
2284 {	/* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1${p}.32	$vd, $rn! */
2287 {	/* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1${p}.32	$vd, $rn, $rm */
2290 {	/* ARM_VLD1d32T, ARM_INS_VLD1: vld1${p}.32	$vd, $rn */
2293 {	/* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1${p}.32	$vd, $rn! */
2296 {	/* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1${p}.32	$vd, $rn, $rm */
2299 {	/* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1${p}.32	$vd, $rn! */
2302 {	/* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1${p}.32	$vd, $rn, $rm */
2305 {	/* ARM_VLD1d64, ARM_INS_VLD1: vld1${p}.64	$vd, $rn */
2308 {	/* ARM_VLD1d64Q, ARM_INS_VLD1: vld1${p}.64	$vd, $rn */
2311 {	/* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1${p}.64	$vd, $rn! */
2314 {	/* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1${p}.64	$vd, $rn, $rm */
2317 {	/* ARM_VLD1d64T, ARM_INS_VLD1: vld1${p}.64	$vd, $rn */
2320 {	/* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1${p}.64	$vd, $rn! */
2323 {	/* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1${p}.64	$vd, $rn, $rm */
2326 {	/* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1${p}.64	$vd, $rn! */
2329 {	/* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1${p}.64	$vd, $rn, $rm */
2332 {	/* ARM_VLD1d8, ARM_INS_VLD1: vld1${p}.8	$vd, $rn */
2335 {	/* ARM_VLD1d8Q, ARM_INS_VLD1: vld1${p}.8	$vd, $rn */
2338 {	/* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1${p}.8	$vd, $rn! */
2341 {	/* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1${p}.8	$vd, $rn, $rm */
2344 {	/* ARM_VLD1d8T, ARM_INS_VLD1: vld1${p}.8	$vd, $rn */
2347 {	/* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1${p}.8	$vd, $rn! */
2350 {	/* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1${p}.8	$vd, $rn, $rm */
2353 {	/* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1${p}.8	$vd, $rn! */
2356 {	/* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1${p}.8	$vd, $rn, $rm */
2359 {	/* ARM_VLD1q16, ARM_INS_VLD1: vld1${p}.16	$vd, $rn */
2362 {	/* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1${p}.16	$vd, $rn! */
2365 {	/* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1${p}.16	$vd, $rn, $rm */
2368 {	/* ARM_VLD1q32, ARM_INS_VLD1: vld1${p}.32	$vd, $rn */
2371 {	/* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1${p}.32	$vd, $rn! */
2374 {	/* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1${p}.32	$vd, $rn, $rm */
2377 {	/* ARM_VLD1q64, ARM_INS_VLD1: vld1${p}.64	$vd, $rn */
2380 {	/* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1${p}.64	$vd, $rn! */
2383 {	/* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1${p}.64	$vd, $rn, $rm */
2386 {	/* ARM_VLD1q8, ARM_INS_VLD1: vld1${p}.8	$vd, $rn */
2389 {	/* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1${p}.8	$vd, $rn! */
2392 {	/* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1${p}.8	$vd, $rn, $rm */
2395 {	/* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2${p}.16	$vd, $rn */
2398 {	/* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2${p}.16	$vd, $rn! */
2401 {	/* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2${p}.16	$vd, $rn, $rm */
2404 {	/* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2${p}.16	$vd, $rn */
2407 {	/* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2${p}.16	$vd, $rn! */
2410 {	/* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2${p}.16	$vd, $rn, $rm */
2413 {	/* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2${p}.32	$vd, $rn */
2416 {	/* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2${p}.32	$vd, $rn! */
2419 {	/* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2${p}.32	$vd, $rn, $rm */
2422 {	/* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2${p}.32	$vd, $rn */
2425 {	/* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2${p}.32	$vd, $rn! */
2428 {	/* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2${p}.32	$vd, $rn, $rm */
2431 {	/* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2${p}.8	$vd, $rn */
2434 {	/* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2${p}.8	$vd, $rn! */
2437 {	/* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2${p}.8	$vd, $rn, $rm */
2440 {	/* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2${p}.8	$vd, $rn */
2443 {	/* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2${p}.8	$vd, $rn! */
2446 {	/* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2${p}.8	$vd, $rn, $rm */
2449 {	/* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16	\{$vd[$lane], $dst2[$lane]\}, $rn */
2452 {	/* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16	\{$vd[$lane], $dst2[$lane]\}, $rn$rm */
2455 {	/* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32	\{$vd[$lane], $dst2[$lane]\}, $rn */
2458 {	/* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32	\{$vd[$lane], $dst2[$lane]\}, $rn$rm */
2461 {	/* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8	\{$vd[$lane], $dst2[$lane]\}, $rn */
2464 {	/* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8	\{$vd[$lane], $dst2[$lane]\}, $rn$rm */
2467 {	/* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16	\{$vd[$lane], $dst2[$lane]\}, $rn */
2470 {	/* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16	\{$vd[$lane], $dst2[$lane]\}, $rn$rm */
2473 {	/* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32	\{$vd[$lane], $dst2[$lane]\}, $rn */
2476 {	/* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32	\{$vd[$lane], $dst2[$lane]\}, $rn$rm */
2479 {	/* ARM_VLD2b16, ARM_INS_VLD2: vld2${p}.16	$vd, $rn */
2482 {	/* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2${p}.16	$vd, $rn! */
2485 {	/* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2${p}.16	$vd, $rn, $rm */
2488 {	/* ARM_VLD2b32, ARM_INS_VLD2: vld2${p}.32	$vd, $rn */
2491 {	/* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2${p}.32	$vd, $rn! */
2494 {	/* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2${p}.32	$vd, $rn, $rm */
2497 {	/* ARM_VLD2b8, ARM_INS_VLD2: vld2${p}.8	$vd, $rn */
2500 {	/* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2${p}.8	$vd, $rn! */
2503 {	/* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2${p}.8	$vd, $rn, $rm */
2506 {	/* ARM_VLD2d16, ARM_INS_VLD2: vld2${p}.16	$vd, $rn */
2509 {	/* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2${p}.16	$vd, $rn! */
2512 {	/* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2${p}.16	$vd, $rn, $rm */
2515 {	/* ARM_VLD2d32, ARM_INS_VLD2: vld2${p}.32	$vd, $rn */
2518 {	/* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2${p}.32	$vd, $rn! */
2521 {	/* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2${p}.32	$vd, $rn, $rm */
2524 {	/* ARM_VLD2d8, ARM_INS_VLD2: vld2${p}.8	$vd, $rn */
2527 {	/* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2${p}.8	$vd, $rn! */
2530 {	/* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2${p}.8	$vd, $rn, $rm */
2533 {	/* ARM_VLD2q16, ARM_INS_VLD2: vld2${p}.16	$vd, $rn */
2536 {	/* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2${p}.16	$vd, $rn! */
2539 {	/* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2${p}.16	$vd, $rn, $rm */
2542 {	/* ARM_VLD2q32, ARM_INS_VLD2: vld2${p}.32	$vd, $rn */
2545 {	/* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2${p}.32	$vd, $rn! */
2548 {	/* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2${p}.32	$vd, $rn, $rm */
2551 {	/* ARM_VLD2q8, ARM_INS_VLD2: vld2${p}.8	$vd, $rn */
2554 {	/* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2${p}.8	$vd, $rn! */
2557 {	/* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2${p}.8	$vd, $rn, $rm */
2560 {	/* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16	\{$vd[], $dst2[], $dst3[]\}, $rn */
2563 {	/* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16	\{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2566 {	/* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32	\{$vd[], $dst2[], $dst3[]\}, $rn */
2569 {	/* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32	\{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2572 {	/* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8	\{$vd[], $dst2[], $dst3[]\}, $rn */
2575 {	/* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8	\{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2578 {	/* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16	\{$vd[], $dst2[], $dst3[]\}, $rn */
2581 {	/* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16	\{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2584 {	/* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32	\{$vd[], $dst2[], $dst3[]\}, $rn */
2587 {	/* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32	\{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2590 {	/* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3${p}.8	\{$vd[], $dst2[], $dst3[]\}, $rn */
2593 {	/* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3${p}.8	\{$vd[], $dst2[], $dst3[]\}, $rn$rm */
2596 {	/* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */
2599 {	/* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$r…
2602 {	/* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */
2605 {	/* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$r…
2608 {	/* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */
2611 {	/* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm …
2614 {	/* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */
2617 {	/* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$r…
2620 {	/* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */
2623 {	/* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$r…
2626 {	/* ARM_VLD3d16, ARM_INS_VLD3: vld3${p}.16	\{$vd, $dst2, $dst3\}, $rn */
2629 {	/* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3${p}.16	\{$vd, $dst2, $dst3\}, $rn$rm */
2632 {	/* ARM_VLD3d32, ARM_INS_VLD3: vld3${p}.32	\{$vd, $dst2, $dst3\}, $rn */
2635 {	/* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3${p}.32	\{$vd, $dst2, $dst3\}, $rn$rm */
2638 {	/* ARM_VLD3d8, ARM_INS_VLD3: vld3${p}.8	\{$vd, $dst2, $dst3\}, $rn */
2641 {	/* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3${p}.8	\{$vd, $dst2, $dst3\}, $rn$rm */
2644 {	/* ARM_VLD3q16, ARM_INS_VLD3: vld3${p}.16	\{$vd, $dst2, $dst3\}, $rn */
2647 {	/* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3${p}.16	\{$vd, $dst2, $dst3\}, $rn$rm */
2650 {	/* ARM_VLD3q32, ARM_INS_VLD3: vld3${p}.32	\{$vd, $dst2, $dst3\}, $rn */
2653 {	/* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3${p}.32	\{$vd, $dst2, $dst3\}, $rn$rm */
2656 {	/* ARM_VLD3q8, ARM_INS_VLD3: vld3${p}.8	\{$vd, $dst2, $dst3\}, $rn */
2659 {	/* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3${p}.8	\{$vd, $dst2, $dst3\}, $rn$rm */
2662 {	/* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4${p}.16	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */
2665 {	/* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4${p}.16	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */
2668 {	/* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4${p}.32	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */
2671 {	/* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4${p}.32	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */
2674 {	/* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4${p}.8	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */
2677 {	/* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4${p}.8	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */
2680 {	/* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4${p}.16	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */
2683 {	/* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4${p}.16	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */
2686 {	/* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4${p}.32	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */
2689 {	/* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4${p}.32	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */
2692 {	/* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4${p}.8	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */
2695 {	/* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4${p}.8	\{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */
2698 {	/* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane…
2701 {	/* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$…
2704 {	/* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane…
2707 {	/* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$…
2710 {	/* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\…
2713 {	/* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$la…
2716 {	/* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane…
2719 {	/* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$…
2722 {	/* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane…
2725 {	/* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32	\{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$…
2728 {	/* ARM_VLD4d16, ARM_INS_VLD4: vld4${p}.16	\{$vd, $dst2, $dst3, $dst4\}, $rn */
2731 {	/* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4${p}.16	\{$vd, $dst2, $dst3, $dst4\}, $rn$rm */
2734 {	/* ARM_VLD4d32, ARM_INS_VLD4: vld4${p}.32	\{$vd, $dst2, $dst3, $dst4\}, $rn */
2737 {	/* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4${p}.32	\{$vd, $dst2, $dst3, $dst4\}, $rn$rm */
2740 {	/* ARM_VLD4d8, ARM_INS_VLD4: vld4${p}.8	\{$vd, $dst2, $dst3, $dst4\}, $rn */
2743 {	/* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4${p}.8	\{$vd, $dst2, $dst3, $dst4\}, $rn$rm */
2746 {	/* ARM_VLD4q16, ARM_INS_VLD4: vld4${p}.16	\{$vd, $dst2, $dst3, $dst4\}, $rn */
2749 {	/* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4${p}.16	\{$vd, $dst2, $dst3, $dst4\}, $rn$rm */
2752 {	/* ARM_VLD4q32, ARM_INS_VLD4: vld4${p}.32	\{$vd, $dst2, $dst3, $dst4\}, $rn */
2755 {	/* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4${p}.32	\{$vd, $dst2, $dst3, $dst4\}, $rn$rm */
2758 {	/* ARM_VLD4q8, ARM_INS_VLD4: vld4${p}.8	\{$vd, $dst2, $dst3, $dst4\}, $rn */
2761 {	/* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4${p}.8	\{$vd, $dst2, $dst3, $dst4\}, $rn$rm */
2791 {	/* ARM_VMAXNMND, ARM_INS_VMAXNM: vmaxnm.f32	$vd, $vn, $vm */
2794 {	/* ARM_VMAXNMNQ, ARM_INS_VMAXNM: vmaxnm.f32	$vd, $vn, $vm */
2800 {	/* ARM_VMAXfd, ARM_INS_VMAX: vmax${p}.f32	$vd, $vn, $vm */
2803 {	/* ARM_VMAXfq, ARM_INS_VMAX: vmax${p}.f32	$vd, $vn, $vm */
2806 {	/* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax${p}.s8	$vd, $vn, $vm */
2809 {	/* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax${p}.s32	$vd, $vn, $vm */
2812 {	/* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax${p}.s16	$vd, $vn, $vm */
2815 {	/* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax${p}.s32	$vd, $vn, $vm */
2818 {	/* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax${p}.s16	$vd, $vn, $vm */
2821 {	/* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax${p}.s8	$vd, $vn, $vm */
2824 {	/* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax${p}.u8	$vd, $vn, $vm */
2827 {	/* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax${p}.u32	$vd, $vn, $vm */
2830 {	/* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax${p}.u16	$vd, $vn, $vm */
2833 {	/* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax${p}.u32	$vd, $vn, $vm */
2836 {	/* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax${p}.u16	$vd, $vn, $vm */
2839 {	/* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax${p}.u8	$vd, $vn, $vm */
2845 {	/* ARM_VMINNMND, ARM_INS_VMINNM: vminnm.f32	$vd, $vn, $vm */
2848 {	/* ARM_VMINNMNQ, ARM_INS_VMINNM: vminnm.f32	$vd, $vn, $vm */
2854 {	/* ARM_VMINfd, ARM_INS_VMIN: vmin${p}.f32	$vd, $vn, $vm */
2857 {	/* ARM_VMINfq, ARM_INS_VMIN: vmin${p}.f32	$vd, $vn, $vm */
2860 {	/* ARM_VMINsv16i8, ARM_INS_VMIN: vmin${p}.s8	$vd, $vn, $vm */
2863 {	/* ARM_VMINsv2i32, ARM_INS_VMIN: vmin${p}.s32	$vd, $vn, $vm */
2866 {	/* ARM_VMINsv4i16, ARM_INS_VMIN: vmin${p}.s16	$vd, $vn, $vm */
2869 {	/* ARM_VMINsv4i32, ARM_INS_VMIN: vmin${p}.s32	$vd, $vn, $vm */
2872 {	/* ARM_VMINsv8i16, ARM_INS_VMIN: vmin${p}.s16	$vd, $vn, $vm */
2875 {	/* ARM_VMINsv8i8, ARM_INS_VMIN: vmin${p}.s8	$vd, $vn, $vm */
2878 {	/* ARM_VMINuv16i8, ARM_INS_VMIN: vmin${p}.u8	$vd, $vn, $vm */
2881 {	/* ARM_VMINuv2i32, ARM_INS_VMIN: vmin${p}.u32	$vd, $vn, $vm */
2884 {	/* ARM_VMINuv4i16, ARM_INS_VMIN: vmin${p}.u16	$vd, $vn, $vm */
2887 {	/* ARM_VMINuv4i32, ARM_INS_VMIN: vmin${p}.u32	$vd, $vn, $vm */
2890 {	/* ARM_VMINuv8i16, ARM_INS_VMIN: vmin${p}.u16	$vd, $vn, $vm */
2893 {	/* ARM_VMINuv8i8, ARM_INS_VMIN: vmin${p}.u8	$vd, $vn, $vm */
2899 {	/* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal${p}.s32	$vd, $vn, $vm$lane */
2902 {	/* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal${p}.s16	$vd, $vn, $vm$lane */
2905 {	/* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal${p}.u32	$vd, $vn, $vm$lane */
2908 {	/* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal${p}.u16	$vd, $vn, $vm$lane */
2911 {	/* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal${p}.s32	$vd, $vn, $vm */
2914 {	/* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal${p}.s16	$vd, $vn, $vm */
2917 {	/* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal${p}.s8	$vd, $vn, $vm */
2920 {	/* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal${p}.u32	$vd, $vn, $vm */
2923 {	/* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal${p}.u16	$vd, $vn, $vm */
2926 {	/* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal${p}.u8	$vd, $vn, $vm */
2932 {	/* ARM_VMLAfd, ARM_INS_VMLA: vmla${p}.f32	$vd, $vn, $vm */
2935 {	/* ARM_VMLAfq, ARM_INS_VMLA: vmla${p}.f32	$vd, $vn, $vm */
2938 {	/* ARM_VMLAslfd, ARM_INS_VMLA: vmla${p}.f32	$vd, $vn, $vm$lane */
2941 {	/* ARM_VMLAslfq, ARM_INS_VMLA: vmla${p}.f32	$vd, $vn, $vm$lane */
2944 {	/* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla${p}.i32	$vd, $vn, $vm$lane */
2947 {	/* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla${p}.i16	$vd, $vn, $vm$lane */
2950 {	/* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla${p}.i32	$vd, $vn, $vm$lane */
2953 {	/* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla${p}.i16	$vd, $vn, $vm$lane */
2956 {	/* ARM_VMLAv16i8, ARM_INS_VMLA: vmla${p}.i8	$vd, $vn, $vm */
2959 {	/* ARM_VMLAv2i32, ARM_INS_VMLA: vmla${p}.i32	$vd, $vn, $vm */
2962 {	/* ARM_VMLAv4i16, ARM_INS_VMLA: vmla${p}.i16	$vd, $vn, $vm */
2965 {	/* ARM_VMLAv4i32, ARM_INS_VMLA: vmla${p}.i32	$vd, $vn, $vm */
2968 {	/* ARM_VMLAv8i16, ARM_INS_VMLA: vmla${p}.i16	$vd, $vn, $vm */
2971 {	/* ARM_VMLAv8i8, ARM_INS_VMLA: vmla${p}.i8	$vd, $vn, $vm */
2977 {	/* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl${p}.s32	$vd, $vn, $vm$lane */
2980 {	/* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl${p}.s16	$vd, $vn, $vm$lane */
2983 {	/* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl${p}.u32	$vd, $vn, $vm$lane */
2986 {	/* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl${p}.u16	$vd, $vn, $vm$lane */
2989 {	/* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl${p}.s32	$vd, $vn, $vm */
2992 {	/* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl${p}.s16	$vd, $vn, $vm */
2995 {	/* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl${p}.s8	$vd, $vn, $vm */
2998 {	/* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl${p}.u32	$vd, $vn, $vm */
3001 {	/* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl${p}.u16	$vd, $vn, $vm */
3004 {	/* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl${p}.u8	$vd, $vn, $vm */
3010 {	/* ARM_VMLSfd, ARM_INS_VMLS: vmls${p}.f32	$vd, $vn, $vm */
3013 {	/* ARM_VMLSfq, ARM_INS_VMLS: vmls${p}.f32	$vd, $vn, $vm */
3016 {	/* ARM_VMLSslfd, ARM_INS_VMLS: vmls${p}.f32	$vd, $vn, $vm$lane */
3019 {	/* ARM_VMLSslfq, ARM_INS_VMLS: vmls${p}.f32	$vd, $vn, $vm$lane */
3022 {	/* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls${p}.i32	$vd, $vn, $vm$lane */
3025 {	/* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls${p}.i16	$vd, $vn, $vm$lane */
3028 {	/* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls${p}.i32	$vd, $vn, $vm$lane */
3031 {	/* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls${p}.i16	$vd, $vn, $vm$lane */
3034 {	/* ARM_VMLSv16i8, ARM_INS_VMLS: vmls${p}.i8	$vd, $vn, $vm */
3037 {	/* ARM_VMLSv2i32, ARM_INS_VMLS: vmls${p}.i32	$vd, $vn, $vm */
3040 {	/* ARM_VMLSv4i16, ARM_INS_VMLS: vmls${p}.i16	$vd, $vn, $vm */
3043 {	/* ARM_VMLSv4i32, ARM_INS_VMLS: vmls${p}.i32	$vd, $vn, $vm */
3046 {	/* ARM_VMLSv8i16, ARM_INS_VMLS: vmls${p}.i16	$vd, $vn, $vm */
3049 {	/* ARM_VMLSv8i8, ARM_INS_VMLS: vmls${p}.i8	$vd, $vn, $vm */
3058 {	/* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl${p}.s32	$vd, $vm */
3061 {	/* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl${p}.s16	$vd, $vm */
3064 {	/* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl${p}.s8	$vd, $vm */
3067 {	/* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl${p}.u32	$vd, $vm */
3070 {	/* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl${p}.u16	$vd, $vm */
3073 {	/* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl${p}.u8	$vd, $vm */
3076 {	/* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn${p}.i64	$vd, $vm */
3079 {	/* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn${p}.i32	$vd, $vm */
3082 {	/* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn${p}.i16	$vd, $vm */
3103 {	/* ARM_VMOVv16i8, ARM_INS_VMOV: vmov${p}.i8	$vd, $simm */
3106 {	/* ARM_VMOVv1i64, ARM_INS_VMOV: vmov${p}.i64	$vd, $simm */
3109 {	/* ARM_VMOVv2f32, ARM_INS_VMOV: vmov${p}.f32	$vd, $simm */
3112 {	/* ARM_VMOVv2i32, ARM_INS_VMOV: vmov${p}.i32	$vd, $simm */
3115 {	/* ARM_VMOVv2i64, ARM_INS_VMOV: vmov${p}.i64	$vd, $simm */
3118 {	/* ARM_VMOVv4f32, ARM_INS_VMOV: vmov${p}.f32	$vd, $simm */
3121 {	/* ARM_VMOVv4i16, ARM_INS_VMOV: vmov${p}.i16	$vd, $simm */
3124 {	/* ARM_VMOVv4i32, ARM_INS_VMOV: vmov${p}.i32	$vd, $simm */
3127 {	/* ARM_VMOVv8i16, ARM_INS_VMOV: vmov${p}.i16	$vd, $simm */
3130 {	/* ARM_VMOVv8i8, ARM_INS_VMOV: vmov${p}.i8	$vd, $simm */
3175 {	/* ARM_VMULLp64, ARM_INS_VMULL: vmull.p64	$vd, $vn, $vm */
3178 {	/* ARM_VMULLp8, ARM_INS_VMULL: vmull${p}.p8	$vd, $vn, $vm */
3181 {	/* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull${p}.s32	$vd, $vn, $vm$lane */
3184 {	/* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull${p}.s16	$vd, $vn, $vm$lane */
3187 {	/* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull${p}.u32	$vd, $vn, $vm$lane */
3190 {	/* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull${p}.u16	$vd, $vn, $vm$lane */
3193 {	/* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull${p}.s32	$vd, $vn, $vm */
3196 {	/* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull${p}.s16	$vd, $vn, $vm */
3199 {	/* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull${p}.s8	$vd, $vn, $vm */
3202 {	/* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull${p}.u32	$vd, $vn, $vm */
3205 {	/* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull${p}.u16	$vd, $vn, $vm */
3208 {	/* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull${p}.u8	$vd, $vn, $vm */
3214 {	/* ARM_VMULfd, ARM_INS_VMUL: vmul${p}.f32	$vd, $vn, $vm */
3217 {	/* ARM_VMULfq, ARM_INS_VMUL: vmul${p}.f32	$vd, $vn, $vm */
3220 {	/* ARM_VMULpd, ARM_INS_VMUL: vmul${p}.p8	$vd, $vn, $vm */
3223 {	/* ARM_VMULpq, ARM_INS_VMUL: vmul${p}.p8	$vd, $vn, $vm */
3226 {	/* ARM_VMULslfd, ARM_INS_VMUL: vmul${p}.f32	$vd, $vn, $vm$lane */
3229 {	/* ARM_VMULslfq, ARM_INS_VMUL: vmul${p}.f32	$vd, $vn, $vm$lane */
3232 {	/* ARM_VMULslv2i32, ARM_INS_VMUL: vmul${p}.i32	$vd, $vn, $vm$lane */
3235 {	/* ARM_VMULslv4i16, ARM_INS_VMUL: vmul${p}.i16	$vd, $vn, $vm$lane */
3238 {	/* ARM_VMULslv4i32, ARM_INS_VMUL: vmul${p}.i32	$vd, $vn, $vm$lane */
3241 {	/* ARM_VMULslv8i16, ARM_INS_VMUL: vmul${p}.i16	$vd, $vn, $vm$lane */
3244 {	/* ARM_VMULv16i8, ARM_INS_VMUL: vmul${p}.i8	$vd, $vn, $vm */
3247 {	/* ARM_VMULv2i32, ARM_INS_VMUL: vmul${p}.i32	$vd, $vn, $vm */
3250 {	/* ARM_VMULv4i16, ARM_INS_VMUL: vmul${p}.i16	$vd, $vn, $vm */
3253 {	/* ARM_VMULv4i32, ARM_INS_VMUL: vmul${p}.i32	$vd, $vn, $vm */
3256 {	/* ARM_VMULv8i16, ARM_INS_VMUL: vmul${p}.i16	$vd, $vn, $vm */
3259 {	/* ARM_VMULv8i8, ARM_INS_VMUL: vmul${p}.i8	$vd, $vn, $vm */
3262 {	/* ARM_VMVNd, ARM_INS_VMVN: vmvn${p}	$vd, $vm */
3265 {	/* ARM_VMVNq, ARM_INS_VMVN: vmvn${p}	$vd, $vm */
3268 {	/* ARM_VMVNv2i32, ARM_INS_VMVN: vmvn${p}.i32	$vd, $simm */
3271 {	/* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn${p}.i16	$vd, $simm */
3274 {	/* ARM_VMVNv4i32, ARM_INS_VMVN: vmvn${p}.i32	$vd, $simm */
3277 {	/* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn${p}.i16	$vd, $simm */
3286 {	/* ARM_VNEGf32q, ARM_INS_VNEG: vneg${p}.f32	$vd, $vm */
3289 {	/* ARM_VNEGfd, ARM_INS_VNEG: vneg${p}.f32	$vd, $vm */
3292 {	/* ARM_VNEGs16d, ARM_INS_VNEG: vneg${p}.s16	$vd, $vm */
3295 {	/* ARM_VNEGs16q, ARM_INS_VNEG: vneg${p}.s16	$vd, $vm */
3298 {	/* ARM_VNEGs32d, ARM_INS_VNEG: vneg${p}.s32	$vd, $vm */
3301 {	/* ARM_VNEGs32q, ARM_INS_VNEG: vneg${p}.s32	$vd, $vm */
3304 {	/* ARM_VNEGs8d, ARM_INS_VNEG: vneg${p}.s8	$vd, $vm */
3307 {	/* ARM_VNEGs8q, ARM_INS_VNEG: vneg${p}.s8	$vd, $vm */
3328 {	/* ARM_VORNd, ARM_INS_VORN: vorn${p}	$vd, $vn, $vm */
3331 {	/* ARM_VORNq, ARM_INS_VORN: vorn${p}	$vd, $vn, $vm */
3334 {	/* ARM_VORRd, ARM_INS_VORR: vorr${p}	$vd, $vn, $vm */
3337 {	/* ARM_VORRiv2i32, ARM_INS_VORR: vorr${p}.i32	$vd, $simm */
3340 {	/* ARM_VORRiv4i16, ARM_INS_VORR: vorr${p}.i16	$vd, $simm */
3343 {	/* ARM_VORRiv4i32, ARM_INS_VORR: vorr${p}.i32	$vd, $simm */
3346 {	/* ARM_VORRiv8i16, ARM_INS_VORR: vorr${p}.i16	$vd, $simm */
3349 {	/* ARM_VORRq, ARM_INS_VORR: vorr${p}	$vd, $vn, $vm */
3352 {	/* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal${p}.s8	$vd, $vm */
3355 {	/* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal${p}.s32	$vd, $vm */
3358 {	/* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal${p}.s16	$vd, $vm */
3361 {	/* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal${p}.s32	$vd, $vm */
3364 {	/* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal${p}.s16	$vd, $vm */
3367 {	/* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal${p}.s8	$vd, $vm */
3370 {	/* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal${p}.u8	$vd, $vm */
3373 {	/* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal${p}.u32	$vd, $vm */
3376 {	/* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal${p}.u16	$vd, $vm */
3379 {	/* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal${p}.u32	$vd, $vm */
3382 {	/* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal${p}.u16	$vd, $vm */
3385 {	/* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal${p}.u8	$vd, $vm */
3388 {	/* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl${p}.s8	$vd, $vm */
3391 {	/* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl${p}.s32	$vd, $vm */
3394 {	/* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl${p}.s16	$vd, $vm */
3397 {	/* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl${p}.s32	$vd, $vm */
3400 {	/* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl${p}.s16	$vd, $vm */
3403 {	/* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl${p}.s8	$vd, $vm */
3406 {	/* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl${p}.u8	$vd, $vm */
3409 {	/* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl${p}.u32	$vd, $vm */
3412 {	/* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl${p}.u16	$vd, $vm */
3415 {	/* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl${p}.u32	$vd, $vm */
3418 {	/* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl${p}.u16	$vd, $vm */
3421 {	/* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl${p}.u8	$vd, $vm */
3424 {	/* ARM_VPADDf, ARM_INS_VPADD: vpadd${p}.f32	$vd, $vn, $vm */
3427 {	/* ARM_VPADDi16, ARM_INS_VPADD: vpadd${p}.i16	$vd, $vn, $vm */
3430 {	/* ARM_VPADDi32, ARM_INS_VPADD: vpadd${p}.i32	$vd, $vn, $vm */
3433 {	/* ARM_VPADDi8, ARM_INS_VPADD: vpadd${p}.i8	$vd, $vn, $vm */
3436 {	/* ARM_VPMAXf, ARM_INS_VPMAX: vpmax${p}.f32	$vd, $vn, $vm */
3439 {	/* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax${p}.s16	$vd, $vn, $vm */
3442 {	/* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax${p}.s32	$vd, $vn, $vm */
3445 {	/* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax${p}.s8	$vd, $vn, $vm */
3448 {	/* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax${p}.u16	$vd, $vn, $vm */
3451 {	/* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax${p}.u32	$vd, $vn, $vm */
3454 {	/* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax${p}.u8	$vd, $vn, $vm */
3457 {	/* ARM_VPMINf, ARM_INS_VPMIN: vpmin${p}.f32	$vd, $vn, $vm */
3460 {	/* ARM_VPMINs16, ARM_INS_VPMIN: vpmin${p}.s16	$vd, $vn, $vm */
3463 {	/* ARM_VPMINs32, ARM_INS_VPMIN: vpmin${p}.s32	$vd, $vn, $vm */
3466 {	/* ARM_VPMINs8, ARM_INS_VPMIN: vpmin${p}.s8	$vd, $vn, $vm */
3469 {	/* ARM_VPMINu16, ARM_INS_VPMIN: vpmin${p}.u16	$vd, $vn, $vm */
3472 {	/* ARM_VPMINu32, ARM_INS_VPMIN: vpmin${p}.u32	$vd, $vn, $vm */
3475 {	/* ARM_VPMINu8, ARM_INS_VPMIN: vpmin${p}.u8	$vd, $vn, $vm */
3478 {	/* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs${p}.s8	$vd, $vm */
3481 {	/* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs${p}.s32	$vd, $vm */
3484 {	/* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs${p}.s16	$vd, $vm */
3487 {	/* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs${p}.s32	$vd, $vm */
3490 {	/* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs${p}.s16	$vd, $vm */
3493 {	/* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs${p}.s8	$vd, $vm */
3496 {	/* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd${p}.s8	$vd, $vn, $vm */
3499 {	/* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd${p}.s64	$vd, $vn, $vm */
3502 {	/* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd${p}.s32	$vd, $vn, $vm */
3505 {	/* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd${p}.s64	$vd, $vn, $vm */
3508 {	/* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd${p}.s16	$vd, $vn, $vm */
3511 {	/* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd${p}.s32	$vd, $vn, $vm */
3514 {	/* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd${p}.s16	$vd, $vn, $vm */
3517 {	/* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd${p}.s8	$vd, $vn, $vm */
3520 {	/* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd${p}.u8	$vd, $vn, $vm */
3523 {	/* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd${p}.u64	$vd, $vn, $vm */
3526 {	/* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd${p}.u32	$vd, $vn, $vm */
3529 {	/* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd${p}.u64	$vd, $vn, $vm */
3532 {	/* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd${p}.u16	$vd, $vn, $vm */
3535 {	/* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd${p}.u32	$vd, $vn, $vm */
3538 {	/* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd${p}.u16	$vd, $vn, $vm */
3541 {	/* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd${p}.u8	$vd, $vn, $vm */
3544 {	/* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal${p}.s32	$vd, $vn, $vm$lane */
3547 {	/* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal${p}.s16	$vd, $vn, $vm$lane */
3550 {	/* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal${p}.s32	$vd, $vn, $vm */
3553 {	/* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal${p}.s16	$vd, $vn, $vm */
3556 {	/* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s32	$vd, $vn, $vm$lane */
3559 {	/* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl${p}.s16	$vd, $vn, $vm$lane */
3562 {	/* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl${p}.s32	$vd, $vn, $vm */
3565 {	/* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s16	$vd, $vn, $vm */
3568 {	/* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32	$vd, $vn, $vm$lane */
3571 {	/* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16	$vd, $vn, $vm$lane */
3574 {	/* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32	$vd, $vn, $vm$lane */
3577 {	/* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16	$vd, $vn, $vm$lane */
3580 {	/* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32	$vd, $vn, $vm */
3583 {	/* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16	$vd, $vn, $vm */
3586 {	/* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32	$vd, $vn, $vm */
3589 {	/* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16	$vd, $vn, $vm */
3592 {	/* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull${p}.s32	$vd, $vn, $vm$lane */
3595 {	/* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull${p}.s16	$vd, $vn, $vm$lane */
3598 {	/* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull${p}.s32	$vd, $vn, $vm */
3601 {	/* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull${p}.s16	$vd, $vn, $vm */
3604 {	/* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun${p}.s64	$vd, $vm */
3607 {	/* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun${p}.s32	$vd, $vm */
3610 {	/* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun${p}.s16	$vd, $vm */
3613 {	/* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn${p}.s64	$vd, $vm */
3616 {	/* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn${p}.s32	$vd, $vm */
3619 {	/* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn${p}.s16	$vd, $vm */
3622 {	/* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn${p}.u64	$vd, $vm */
3625 {	/* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn${p}.u32	$vd, $vm */
3628 {	/* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn${p}.u16	$vd, $vm */
3631 {	/* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg${p}.s8	$vd, $vm */
3634 {	/* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg${p}.s32	$vd, $vm */
3637 {	/* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg${p}.s16	$vd, $vm */
3640 {	/* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg${p}.s32	$vd, $vm */
3643 {	/* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg${p}.s16	$vd, $vm */
3646 {	/* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg${p}.s8	$vd, $vm */
3649 {	/* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32	$vd, $vn, $vm$lane */
3652 {	/* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16	$vd, $vn, $vm$lane */
3655 {	/* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32	$vd, $vn, $vm$lane */
3658 {	/* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16	$vd, $vn, $vm$lane */
3661 {	/* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32	$vd, $vn, $vm */
3664 {	/* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16	$vd, $vn, $vm */
3667 {	/* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32	$vd, $vn, $vm */
3670 {	/* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16	$vd, $vn, $vm */
3673 {	/* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl${p}.s8	$vd, $vm, $vn */
3676 {	/* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl${p}.s64	$vd, $vm, $vn */
3679 {	/* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl${p}.s32	$vd, $vm, $vn */
3682 {	/* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl${p}.s64	$vd, $vm, $vn */
3685 {	/* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl${p}.s16	$vd, $vm, $vn */
3688 {	/* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl${p}.s32	$vd, $vm, $vn */
3691 {	/* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl${p}.s16	$vd, $vm, $vn */
3694 {	/* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl${p}.s8	$vd, $vm, $vn */
3697 {	/* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl${p}.u8	$vd, $vm, $vn */
3700 {	/* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl${p}.u64	$vd, $vm, $vn */
3703 {	/* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl${p}.u32	$vd, $vm, $vn */
3706 {	/* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl${p}.u64	$vd, $vm, $vn */
3709 {	/* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl${p}.u16	$vd, $vm, $vn */
3712 {	/* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl${p}.u32	$vd, $vm, $vn */
3715 {	/* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl${p}.u16	$vd, $vm, $vn */
3718 {	/* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl${p}.u8	$vd, $vm, $vn */
3721 {	/* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.s64	$vd, $vm, $simm */
3724 {	/* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.s32	$vd, $vm, $simm */
3727 {	/* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.s16	$vd, $vm, $simm */
3730 {	/* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.u64	$vd, $vm, $simm */
3733 {	/* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.u32	$vd, $vm, $simm */
3736 {	/* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.u16	$vd, $vm, $simm */
3739 {	/* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun${p}.s64	$vd, $vm, $simm */
3742 {	/* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun${p}.s32	$vd, $vm, $simm */
3745 {	/* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun${p}.s16	$vd, $vm, $simm */
3748 {	/* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8	$vd, $vm, $simm */
3751 {	/* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64	$vd, $vm, $simm */
3754 {	/* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32	$vd, $vm, $simm */
3757 {	/* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64	$vd, $vm, $simm */
3760 {	/* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16	$vd, $vm, $simm */
3763 {	/* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32	$vd, $vm, $simm */
3766 {	/* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16	$vd, $vm, $simm */
3769 {	/* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8	$vd, $vm, $simm */
3772 {	/* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu${p}.s8	$vd, $vm, $simm */
3775 {	/* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu${p}.s64	$vd, $vm, $simm */
3778 {	/* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu${p}.s32	$vd, $vm, $simm */
3781 {	/* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu${p}.s64	$vd, $vm, $simm */
3784 {	/* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu${p}.s16	$vd, $vm, $simm */
3787 {	/* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu${p}.s32	$vd, $vm, $simm */
3790 {	/* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu${p}.s16	$vd, $vm, $simm */
3793 {	/* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu${p}.s8	$vd, $vm, $simm */
3796 {	/* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8	$vd, $vm, $vn */
3799 {	/* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64	$vd, $vm, $vn */
3802 {	/* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl${p}.s32	$vd, $vm, $vn */
3805 {	/* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl${p}.s64	$vd, $vm, $vn */
3808 {	/* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl${p}.s16	$vd, $vm, $vn */
3811 {	/* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl${p}.s32	$vd, $vm, $vn */
3814 {	/* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl${p}.s16	$vd, $vm, $vn */
3817 {	/* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl${p}.s8	$vd, $vm, $vn */
3820 {	/* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl${p}.u8	$vd, $vm, $simm */
3823 {	/* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl${p}.u64	$vd, $vm, $simm */
3826 {	/* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl${p}.u32	$vd, $vm, $simm */
3829 {	/* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl${p}.u64	$vd, $vm, $simm */
3832 {	/* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl${p}.u16	$vd, $vm, $simm */
3835 {	/* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl${p}.u32	$vd, $vm, $simm */
3838 {	/* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl${p}.u16	$vd, $vm, $simm */
3841 {	/* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl${p}.u8	$vd, $vm, $simm */
3844 {	/* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl${p}.u8	$vd, $vm, $vn */
3847 {	/* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl${p}.u64	$vd, $vm, $vn */
3850 {	/* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl${p}.u32	$vd, $vm, $vn */
3853 {	/* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl${p}.u64	$vd, $vm, $vn */
3856 {	/* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl${p}.u16	$vd, $vm, $vn */
3859 {	/* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl${p}.u32	$vd, $vm, $vn */
3862 {	/* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl${p}.u16	$vd, $vm, $vn */
3865 {	/* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl${p}.u8	$vd, $vm, $vn */
3868 {	/* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64	$vd, $vm, $simm */
3871 {	/* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32	$vd, $vm, $simm */
3874 {	/* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16	$vd, $vm, $simm */
3877 {	/* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64	$vd, $vm, $simm */
3880 {	/* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32	$vd, $vm, $simm */
3883 {	/* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16	$vd, $vm, $simm */
3886 {	/* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun${p}.s64	$vd, $vm, $simm */
3889 {	/* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun${p}.s32	$vd, $vm, $simm */
3892 {	/* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun${p}.s16	$vd, $vm, $simm */
3895 {	/* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub${p}.s8	$vd, $vn, $vm */
3898 {	/* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub${p}.s64	$vd, $vn, $vm */
3901 {	/* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub${p}.s32	$vd, $vn, $vm */
3904 {	/* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub${p}.s64	$vd, $vn, $vm */
3907 {	/* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub${p}.s16	$vd, $vn, $vm */
3910 {	/* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub${p}.s32	$vd, $vn, $vm */
3913 {	/* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub${p}.s16	$vd, $vn, $vm */
3916 {	/* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub${p}.s8	$vd, $vn, $vm */
3919 {	/* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub${p}.u8	$vd, $vn, $vm */
3922 {	/* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub${p}.u64	$vd, $vn, $vm */
3925 {	/* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub${p}.u32	$vd, $vn, $vm */
3928 {	/* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub${p}.u64	$vd, $vn, $vm */
3931 {	/* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub${p}.u16	$vd, $vn, $vm */
3934 {	/* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub${p}.u32	$vd, $vn, $vm */
3937 {	/* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub${p}.u16	$vd, $vn, $vm */
3940 {	/* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub${p}.u8	$vd, $vn, $vm */
3943 {	/* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64	$vd, $vn, $vm */
3946 {	/* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32	$vd, $vn, $vm */
3949 {	/* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16	$vd, $vn, $vm */
3952 {	/* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32	$vd, $vm */
3955 {	/* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32	$vd, $vm */
3958 {	/* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32	$vd, $vm */
3961 {	/* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32	$vd, $vm */
3964 {	/* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps${p}.f32	$vd, $vn, $vm */
3967 {	/* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps${p}.f32	$vd, $vn, $vm */
3970 {	/* ARM_VREV16d8, ARM_INS_VREV16: vrev16${p}.8	$vd, $vm */
3973 {	/* ARM_VREV16q8, ARM_INS_VREV16: vrev16${p}.8	$vd, $vm */
3976 {	/* ARM_VREV32d16, ARM_INS_VREV32: vrev32${p}.16	$vd, $vm */
3979 {	/* ARM_VREV32d8, ARM_INS_VREV32: vrev32${p}.8	$vd, $vm */
3982 {	/* ARM_VREV32q16, ARM_INS_VREV32: vrev32${p}.16	$vd, $vm */
3985 {	/* ARM_VREV32q8, ARM_INS_VREV32: vrev32${p}.8	$vd, $vm */
3988 {	/* ARM_VREV64d16, ARM_INS_VREV64: vrev64${p}.16	$vd, $vm */
3991 {	/* ARM_VREV64d32, ARM_INS_VREV64: vrev64${p}.32	$vd, $vm */
3994 {	/* ARM_VREV64d8, ARM_INS_VREV64: vrev64${p}.8	$vd, $vm */
3997 {	/* ARM_VREV64q16, ARM_INS_VREV64: vrev64${p}.16	$vd, $vm */
4000 {	/* ARM_VREV64q32, ARM_INS_VREV64: vrev64${p}.32	$vd, $vm */
4003 {	/* ARM_VREV64q8, ARM_INS_VREV64: vrev64${p}.8	$vd, $vm */
4006 {	/* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd${p}.s8	$vd, $vn, $vm */
4009 {	/* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd${p}.s32	$vd, $vn, $vm */
4012 {	/* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd${p}.s16	$vd, $vn, $vm */
4015 {	/* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd${p}.s32	$vd, $vn, $vm */
4018 {	/* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd${p}.s16	$vd, $vn, $vm */
4021 {	/* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd${p}.s8	$vd, $vn, $vm */
4024 {	/* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd${p}.u8	$vd, $vn, $vm */
4027 {	/* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd${p}.u32	$vd, $vn, $vm */
4030 {	/* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd${p}.u16	$vd, $vn, $vm */
4033 {	/* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd${p}.u32	$vd, $vn, $vm */
4036 {	/* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd${p}.u16	$vd, $vn, $vm */
4039 {	/* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd${p}.u8	$vd, $vn, $vm */
4045 {	/* ARM_VRINTAND, ARM_INS_VRINTA: vrinta.f32	$vd, $vm */
4048 {	/* ARM_VRINTANQ, ARM_INS_VRINTA: vrinta.f32	$vd, $vm */
4057 {	/* ARM_VRINTMND, ARM_INS_VRINTM: vrintm.f32	$vd, $vm */
4060 {	/* ARM_VRINTMNQ, ARM_INS_VRINTM: vrintm.f32	$vd, $vm */
4069 {	/* ARM_VRINTNND, ARM_INS_VRINTN: vrintn.f32	$vd, $vm */
4072 {	/* ARM_VRINTNNQ, ARM_INS_VRINTN: vrintn.f32	$vd, $vm */
4081 {	/* ARM_VRINTPND, ARM_INS_VRINTP: vrintp.f32	$vd, $vm */
4084 {	/* ARM_VRINTPNQ, ARM_INS_VRINTP: vrintp.f32	$vd, $vm */
4099 {	/* ARM_VRINTXND, ARM_INS_VRINTX: vrintx.f32	$vd, $vm */
4102 {	/* ARM_VRINTXNQ, ARM_INS_VRINTX: vrintx.f32	$vd, $vm */
4111 {	/* ARM_VRINTZND, ARM_INS_VRINTZ: vrintz.f32	$vd, $vm */
4114 {	/* ARM_VRINTZNQ, ARM_INS_VRINTZ: vrintz.f32	$vd, $vm */
4120 {	/* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8	$vd, $vm, $vn */
4123 {	/* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64	$vd, $vm, $vn */
4126 {	/* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32	$vd, $vm, $vn */
4129 {	/* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64	$vd, $vm, $vn */
4132 {	/* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16	$vd, $vm, $vn */
4135 {	/* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32	$vd, $vm, $vn */
4138 {	/* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16	$vd, $vm, $vn */
4141 {	/* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8	$vd, $vm, $vn */
4144 {	/* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8	$vd, $vm, $vn */
4147 {	/* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64	$vd, $vm, $vn */
4150 {	/* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl${p}.u32	$vd, $vm, $vn */
4153 {	/* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl${p}.u64	$vd, $vm, $vn */
4156 {	/* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl${p}.u16	$vd, $vm, $vn */
4159 {	/* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl${p}.u32	$vd, $vm, $vn */
4162 {	/* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl${p}.u16	$vd, $vm, $vn */
4165 {	/* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl${p}.u8	$vd, $vm, $vn */
4168 {	/* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn${p}.i64	$vd, $vm, $simm */
4171 {	/* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn${p}.i32	$vd, $vm, $simm */
4174 {	/* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn${p}.i16	$vd, $vm, $simm */
4177 {	/* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr${p}.s8	$vd, $vm, $simm */
4180 {	/* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr${p}.s64	$vd, $vm, $simm */
4183 {	/* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr${p}.s32	$vd, $vm, $simm */
4186 {	/* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr${p}.s64	$vd, $vm, $simm */
4189 {	/* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr${p}.s16	$vd, $vm, $simm */
4192 {	/* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr${p}.s32	$vd, $vm, $simm */
4195 {	/* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr${p}.s16	$vd, $vm, $simm */
4198 {	/* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr${p}.s8	$vd, $vm, $simm */
4201 {	/* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr${p}.u8	$vd, $vm, $simm */
4204 {	/* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr${p}.u64	$vd, $vm, $simm */
4207 {	/* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr${p}.u32	$vd, $vm, $simm */
4210 {	/* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr${p}.u64	$vd, $vm, $simm */
4213 {	/* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr${p}.u16	$vd, $vm, $simm */
4216 {	/* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr${p}.u32	$vd, $vm, $simm */
4219 {	/* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr${p}.u16	$vd, $vm, $simm */
4222 {	/* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr${p}.u8	$vd, $vm, $simm */
4225 {	/* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte${p}.u32	$vd, $vm */
4228 {	/* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte${p}.f32	$vd, $vm */
4231 {	/* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte${p}.f32	$vd, $vm */
4234 {	/* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte${p}.u32	$vd, $vm */
4237 {	/* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts${p}.f32	$vd, $vn, $vm */
4240 {	/* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts${p}.f32	$vd, $vn, $vm */
4243 {	/* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra${p}.s8	$vd, $vm, $simm */
4246 {	/* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra${p}.s64	$vd, $vm, $simm */
4249 {	/* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra${p}.s32	$vd, $vm, $simm */
4252 {	/* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra${p}.s64	$vd, $vm, $simm */
4255 {	/* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra${p}.s16	$vd, $vm, $simm */
4258 {	/* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra${p}.s32	$vd, $vm, $simm */
4261 {	/* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra${p}.s16	$vd, $vm, $simm */
4264 {	/* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra${p}.s8	$vd, $vm, $simm */
4267 {	/* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra${p}.u8	$vd, $vm, $simm */
4270 {	/* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra${p}.u64	$vd, $vm, $simm */
4273 {	/* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra${p}.u32	$vd, $vm, $simm */
4276 {	/* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra${p}.u64	$vd, $vm, $simm */
4279 {	/* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra${p}.u16	$vd, $vm, $simm */
4282 {	/* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra${p}.u32	$vd, $vm, $simm */
4285 {	/* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra${p}.u16	$vd, $vm, $simm */
4288 {	/* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra${p}.u8	$vd, $vm, $simm */
4291 {	/* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn${p}.i64	$vd, $vn, $vm */
4294 {	/* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn${p}.i32	$vd, $vn, $vm */
4297 {	/* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn${p}.i16	$vd, $vn, $vm */
4333 {	/* ARM_VSHLLi16, ARM_INS_VSHLL: vshll${p}.i16	$vd, $vm, $simm */
4336 {	/* ARM_VSHLLi32, ARM_INS_VSHLL: vshll${p}.i32	$vd, $vm, $simm */
4339 {	/* ARM_VSHLLi8, ARM_INS_VSHLL: vshll${p}.i8	$vd, $vm, $simm */
4342 {	/* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll${p}.s32	$vd, $vm, $simm */
4345 {	/* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll${p}.s16	$vd, $vm, $simm */
4348 {	/* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll${p}.s8	$vd, $vm, $simm */
4351 {	/* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll${p}.u32	$vd, $vm, $simm */
4354 {	/* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll${p}.u16	$vd, $vm, $simm */
4357 {	/* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll${p}.u8	$vd, $vm, $simm */
4360 {	/* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl${p}.i8	$vd, $vm, $simm */
4363 {	/* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl${p}.i64	$vd, $vm, $simm */
4366 {	/* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl${p}.i32	$vd, $vm, $simm */
4369 {	/* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl${p}.i64	$vd, $vm, $simm */
4372 {	/* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl${p}.i16	$vd, $vm, $simm */
4375 {	/* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl${p}.i32	$vd, $vm, $simm */
4378 {	/* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl${p}.i16	$vd, $vm, $simm */
4381 {	/* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl${p}.i8	$vd, $vm, $simm */
4384 {	/* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl${p}.s8	$vd, $vm, $vn */
4387 {	/* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl${p}.s64	$vd, $vm, $vn */
4390 {	/* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl${p}.s32	$vd, $vm, $vn */
4393 {	/* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl${p}.s64	$vd, $vm, $vn */
4396 {	/* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl${p}.s16	$vd, $vm, $vn */
4399 {	/* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl${p}.s32	$vd, $vm, $vn */
4402 {	/* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl${p}.s16	$vd, $vm, $vn */
4405 {	/* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl${p}.s8	$vd, $vm, $vn */
4408 {	/* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl${p}.u8	$vd, $vm, $vn */
4411 {	/* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl${p}.u64	$vd, $vm, $vn */
4414 {	/* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl${p}.u32	$vd, $vm, $vn */
4417 {	/* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl${p}.u64	$vd, $vm, $vn */
4420 {	/* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl${p}.u16	$vd, $vm, $vn */
4423 {	/* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl${p}.u32	$vd, $vm, $vn */
4426 {	/* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl${p}.u16	$vd, $vm, $vn */
4429 {	/* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl${p}.u8	$vd, $vm, $vn */
4432 {	/* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn${p}.i64	$vd, $vm, $simm */
4435 {	/* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn${p}.i32	$vd, $vm, $simm */
4438 {	/* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn${p}.i16	$vd, $vm, $simm */
4441 {	/* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8	$vd, $vm, $simm */
4444 {	/* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64	$vd, $vm, $simm */
4447 {	/* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32	$vd, $vm, $simm */
4450 {	/* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64	$vd, $vm, $simm */
4453 {	/* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16	$vd, $vm, $simm */
4456 {	/* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32	$vd, $vm, $simm */
4459 {	/* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16	$vd, $vm, $simm */
4462 {	/* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8	$vd, $vm, $simm */
4465 {	/* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8	$vd, $vm, $simm */
4468 {	/* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64	$vd, $vm, $simm */
4471 {	/* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr${p}.u32	$vd, $vm, $simm */
4474 {	/* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr${p}.u64	$vd, $vm, $simm */
4477 {	/* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr${p}.u16	$vd, $vm, $simm */
4480 {	/* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr${p}.u32	$vd, $vm, $simm */
4483 {	/* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr${p}.u16	$vd, $vm, $simm */
4486 {	/* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr${p}.u8	$vd, $vm, $simm */
4501 {	/* ARM_VSLIv16i8, ARM_INS_VSLI: vsli${p}.8	$vd, $vm, $simm */
4504 {	/* ARM_VSLIv1i64, ARM_INS_VSLI: vsli${p}.64	$vd, $vm, $simm */
4507 {	/* ARM_VSLIv2i32, ARM_INS_VSLI: vsli${p}.32	$vd, $vm, $simm */
4510 {	/* ARM_VSLIv2i64, ARM_INS_VSLI: vsli${p}.64	$vd, $vm, $simm */
4513 {	/* ARM_VSLIv4i16, ARM_INS_VSLI: vsli${p}.16	$vd, $vm, $simm */
4516 {	/* ARM_VSLIv4i32, ARM_INS_VSLI: vsli${p}.32	$vd, $vm, $simm */
4519 {	/* ARM_VSLIv8i16, ARM_INS_VSLI: vsli${p}.16	$vd, $vm, $simm */
4522 {	/* ARM_VSLIv8i8, ARM_INS_VSLI: vsli${p}.8	$vd, $vm, $simm */
4537 {	/* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra${p}.s8	$vd, $vm, $simm */
4540 {	/* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra${p}.s64	$vd, $vm, $simm */
4543 {	/* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra${p}.s32	$vd, $vm, $simm */
4546 {	/* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra${p}.s64	$vd, $vm, $simm */
4549 {	/* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra${p}.s16	$vd, $vm, $simm */
4552 {	/* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra${p}.s32	$vd, $vm, $simm */
4555 {	/* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra${p}.s16	$vd, $vm, $simm */
4558 {	/* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra${p}.s8	$vd, $vm, $simm */
4561 {	/* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra${p}.u8	$vd, $vm, $simm */
4564 {	/* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra${p}.u64	$vd, $vm, $simm */
4567 {	/* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra${p}.u32	$vd, $vm, $simm */
4570 {	/* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra${p}.u64	$vd, $vm, $simm */
4573 {	/* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra${p}.u16	$vd, $vm, $simm */
4576 {	/* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra${p}.u32	$vd, $vm, $simm */
4579 {	/* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra${p}.u16	$vd, $vm, $simm */
4582 {	/* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra${p}.u8	$vd, $vm, $simm */
4585 {	/* ARM_VSRIv16i8, ARM_INS_VSRI: vsri${p}.8	$vd, $vm, $simm */
4588 {	/* ARM_VSRIv1i64, ARM_INS_VSRI: vsri${p}.64	$vd, $vm, $simm */
4591 {	/* ARM_VSRIv2i32, ARM_INS_VSRI: vsri${p}.32	$vd, $vm, $simm */
4594 {	/* ARM_VSRIv2i64, ARM_INS_VSRI: vsri${p}.64	$vd, $vm, $simm */
4597 {	/* ARM_VSRIv4i16, ARM_INS_VSRI: vsri${p}.16	$vd, $vm, $simm */
4600 {	/* ARM_VSRIv4i32, ARM_INS_VSRI: vsri${p}.32	$vd, $vm, $simm */
4603 {	/* ARM_VSRIv8i16, ARM_INS_VSRI: vsri${p}.16	$vd, $vm, $simm */
4606 {	/* ARM_VSRIv8i8, ARM_INS_VSRI: vsri${p}.8	$vd, $vm, $simm */
4609 {	/* ARM_VST1LNd16, ARM_INS_VST1: vst1${p}.16	\{$vd[$lane]\}, $rn */
4612 {	/* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1${p}.16	\{$vd[$lane]\}, $rn$rm */
4615 {	/* ARM_VST1LNd32, ARM_INS_VST1: vst1${p}.32	\{$vd[$lane]\}, $rn */
4618 {	/* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1${p}.32	\{$vd[$lane]\}, $rn$rm */
4621 {	/* ARM_VST1LNd8, ARM_INS_VST1: vst1${p}.8	\{$vd[$lane]\}, $rn */
4624 {	/* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1${p}.8	\{$vd[$lane]\}, $rn$rm */
4627 {	/* ARM_VST1d16, ARM_INS_VST1: vst1${p}.16	$vd, $rn */
4630 {	/* ARM_VST1d16Q, ARM_INS_VST1: vst1${p}.16	$vd, $rn */
4633 {	/* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1${p}.16	$vd, $rn! */
4636 {	/* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1${p}.16	$vd, $rn, $rm */
4639 {	/* ARM_VST1d16T, ARM_INS_VST1: vst1${p}.16	$vd, $rn */
4642 {	/* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1${p}.16	$vd, $rn! */
4645 {	/* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1${p}.16	$vd, $rn, $rm */
4648 {	/* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1${p}.16	$vd, $rn! */
4651 {	/* ARM_VST1d16wb_register, ARM_INS_VST1: vst1${p}.16	$vd, $rn, $rm */
4654 {	/* ARM_VST1d32, ARM_INS_VST1: vst1${p}.32	$vd, $rn */
4657 {	/* ARM_VST1d32Q, ARM_INS_VST1: vst1${p}.32	$vd, $rn */
4660 {	/* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1${p}.32	$vd, $rn! */
4663 {	/* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1${p}.32	$vd, $rn, $rm */
4666 {	/* ARM_VST1d32T, ARM_INS_VST1: vst1${p}.32	$vd, $rn */
4669 {	/* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1${p}.32	$vd, $rn! */
4672 {	/* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1${p}.32	$vd, $rn, $rm */
4675 {	/* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1${p}.32	$vd, $rn! */
4678 {	/* ARM_VST1d32wb_register, ARM_INS_VST1: vst1${p}.32	$vd, $rn, $rm */
4681 {	/* ARM_VST1d64, ARM_INS_VST1: vst1${p}.64	$vd, $rn */
4684 {	/* ARM_VST1d64Q, ARM_INS_VST1: vst1${p}.64	$vd, $rn */
4687 {	/* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1${p}.64	$vd, $rn! */
4690 {	/* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1${p}.64	$vd, $rn, $rm */
4693 {	/* ARM_VST1d64T, ARM_INS_VST1: vst1${p}.64	$vd, $rn */
4696 {	/* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1${p}.64	$vd, $rn! */
4699 {	/* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1${p}.64	$vd, $rn, $rm */
4702 {	/* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1${p}.64	$vd, $rn! */
4705 {	/* ARM_VST1d64wb_register, ARM_INS_VST1: vst1${p}.64	$vd, $rn, $rm */
4708 {	/* ARM_VST1d8, ARM_INS_VST1: vst1${p}.8	$vd, $rn */
4711 {	/* ARM_VST1d8Q, ARM_INS_VST1: vst1${p}.8	$vd, $rn */
4714 {	/* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1${p}.8	$vd, $rn! */
4717 {	/* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1${p}.8	$vd, $rn, $rm */
4720 {	/* ARM_VST1d8T, ARM_INS_VST1: vst1${p}.8	$vd, $rn */
4723 {	/* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1${p}.8	$vd, $rn! */
4726 {	/* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1${p}.8	$vd, $rn, $rm */
4729 {	/* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1${p}.8	$vd, $rn! */
4732 {	/* ARM_VST1d8wb_register, ARM_INS_VST1: vst1${p}.8	$vd, $rn, $rm */
4735 {	/* ARM_VST1q16, ARM_INS_VST1: vst1${p}.16	$vd, $rn */
4738 {	/* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1${p}.16	$vd, $rn! */
4741 {	/* ARM_VST1q16wb_register, ARM_INS_VST1: vst1${p}.16	$vd, $rn, $rm */
4744 {	/* ARM_VST1q32, ARM_INS_VST1: vst1${p}.32	$vd, $rn */
4747 {	/* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1${p}.32	$vd, $rn! */
4750 {	/* ARM_VST1q32wb_register, ARM_INS_VST1: vst1${p}.32	$vd, $rn, $rm */
4753 {	/* ARM_VST1q64, ARM_INS_VST1: vst1${p}.64	$vd, $rn */
4756 {	/* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1${p}.64	$vd, $rn! */
4759 {	/* ARM_VST1q64wb_register, ARM_INS_VST1: vst1${p}.64	$vd, $rn, $rm */
4762 {	/* ARM_VST1q8, ARM_INS_VST1: vst1${p}.8	$vd, $rn */
4765 {	/* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1${p}.8	$vd, $rn! */
4768 {	/* ARM_VST1q8wb_register, ARM_INS_VST1: vst1${p}.8	$vd, $rn, $rm */
4771 {	/* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16	\{$vd[$lane], $src2[$lane]\}, $rn */
4774 {	/* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16	\{$vd[$lane], $src2[$lane]\}, $rn$rm */
4777 {	/* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32	\{$vd[$lane], $src2[$lane]\}, $rn */
4780 {	/* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32	\{$vd[$lane], $src2[$lane]\}, $rn$rm */
4783 {	/* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8	\{$vd[$lane], $src2[$lane]\}, $rn */
4786 {	/* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8	\{$vd[$lane], $src2[$lane]\}, $rn$rm */
4789 {	/* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16	\{$vd[$lane], $src2[$lane]\}, $rn */
4792 {	/* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16	\{$vd[$lane], $src2[$lane]\}, $rn$rm */
4795 {	/* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32	\{$vd[$lane], $src2[$lane]\}, $rn */
4798 {	/* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32	\{$vd[$lane], $src2[$lane]\}, $rn$rm */
4801 {	/* ARM_VST2b16, ARM_INS_VST2: vst2${p}.16	$vd, $rn */
4804 {	/* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2${p}.16	$vd, $rn! */
4807 {	/* ARM_VST2b16wb_register, ARM_INS_VST2: vst2${p}.16	$vd, $rn, $rm */
4810 {	/* ARM_VST2b32, ARM_INS_VST2: vst2${p}.32	$vd, $rn */
4813 {	/* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2${p}.32	$vd, $rn! */
4816 {	/* ARM_VST2b32wb_register, ARM_INS_VST2: vst2${p}.32	$vd, $rn, $rm */
4819 {	/* ARM_VST2b8, ARM_INS_VST2: vst2${p}.8	$vd, $rn */
4822 {	/* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2${p}.8	$vd, $rn! */
4825 {	/* ARM_VST2b8wb_register, ARM_INS_VST2: vst2${p}.8	$vd, $rn, $rm */
4828 {	/* ARM_VST2d16, ARM_INS_VST2: vst2${p}.16	$vd, $rn */
4831 {	/* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2${p}.16	$vd, $rn! */
4834 {	/* ARM_VST2d16wb_register, ARM_INS_VST2: vst2${p}.16	$vd, $rn, $rm */
4837 {	/* ARM_VST2d32, ARM_INS_VST2: vst2${p}.32	$vd, $rn */
4840 {	/* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2${p}.32	$vd, $rn! */
4843 {	/* ARM_VST2d32wb_register, ARM_INS_VST2: vst2${p}.32	$vd, $rn, $rm */
4846 {	/* ARM_VST2d8, ARM_INS_VST2: vst2${p}.8	$vd, $rn */
4849 {	/* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2${p}.8	$vd, $rn! */
4852 {	/* ARM_VST2d8wb_register, ARM_INS_VST2: vst2${p}.8	$vd, $rn, $rm */
4855 {	/* ARM_VST2q16, ARM_INS_VST2: vst2${p}.16	$vd, $rn */
4858 {	/* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2${p}.16	$vd, $rn! */
4861 {	/* ARM_VST2q16wb_register, ARM_INS_VST2: vst2${p}.16	$vd, $rn, $rm */
4864 {	/* ARM_VST2q32, ARM_INS_VST2: vst2${p}.32	$vd, $rn */
4867 {	/* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2${p}.32	$vd, $rn! */
4870 {	/* ARM_VST2q32wb_register, ARM_INS_VST2: vst2${p}.32	$vd, $rn, $rm */
4873 {	/* ARM_VST2q8, ARM_INS_VST2: vst2${p}.8	$vd, $rn */
4876 {	/* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2${p}.8	$vd, $rn! */
4879 {	/* ARM_VST2q8wb_register, ARM_INS_VST2: vst2${p}.8	$vd, $rn, $rm */
4882 {	/* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */
4885 {	/* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$r…
4888 {	/* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */
4891 {	/* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$r…
4894 {	/* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */
4897 {	/* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm …
4900 {	/* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */
4903 {	/* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$r…
4906 {	/* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */
4909 {	/* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$r…
4912 {	/* ARM_VST3d16, ARM_INS_VST3: vst3${p}.16	\{$vd, $src2, $src3\}, $rn */
4915 {	/* ARM_VST3d16_UPD, ARM_INS_VST3: vst3${p}.16	\{$vd, $src2, $src3\}, $rn$rm */
4918 {	/* ARM_VST3d32, ARM_INS_VST3: vst3${p}.32	\{$vd, $src2, $src3\}, $rn */
4921 {	/* ARM_VST3d32_UPD, ARM_INS_VST3: vst3${p}.32	\{$vd, $src2, $src3\}, $rn$rm */
4924 {	/* ARM_VST3d8, ARM_INS_VST3: vst3${p}.8	\{$vd, $src2, $src3\}, $rn */
4927 {	/* ARM_VST3d8_UPD, ARM_INS_VST3: vst3${p}.8	\{$vd, $src2, $src3\}, $rn$rm */
4930 {	/* ARM_VST3q16, ARM_INS_VST3: vst3${p}.16	\{$vd, $src2, $src3\}, $rn */
4933 {	/* ARM_VST3q16_UPD, ARM_INS_VST3: vst3${p}.16	\{$vd, $src2, $src3\}, $rn$rm */
4936 {	/* ARM_VST3q32, ARM_INS_VST3: vst3${p}.32	\{$vd, $src2, $src3\}, $rn */
4939 {	/* ARM_VST3q32_UPD, ARM_INS_VST3: vst3${p}.32	\{$vd, $src2, $src3\}, $rn$rm */
4942 {	/* ARM_VST3q8, ARM_INS_VST3: vst3${p}.8	\{$vd, $src2, $src3\}, $rn */
4945 {	/* ARM_VST3q8_UPD, ARM_INS_VST3: vst3${p}.8	\{$vd, $src2, $src3\}, $rn$rm */
4948 {	/* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane…
4951 {	/* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$…
4954 {	/* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane…
4957 {	/* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$…
4960 {	/* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\…
4963 {	/* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$la…
4966 {	/* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane…
4969 {	/* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$…
4972 {	/* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane…
4975 {	/* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32	\{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$…
4978 {	/* ARM_VST4d16, ARM_INS_VST4: vst4${p}.16	\{$vd, $src2, $src3, $src4\}, $rn */
4981 {	/* ARM_VST4d16_UPD, ARM_INS_VST4: vst4${p}.16	\{$vd, $src2, $src3, $src4\}, $rn$rm */
4984 {	/* ARM_VST4d32, ARM_INS_VST4: vst4${p}.32	\{$vd, $src2, $src3, $src4\}, $rn */
4987 {	/* ARM_VST4d32_UPD, ARM_INS_VST4: vst4${p}.32	\{$vd, $src2, $src3, $src4\}, $rn$rm */
4990 {	/* ARM_VST4d8, ARM_INS_VST4: vst4${p}.8	\{$vd, $src2, $src3, $src4\}, $rn */
4993 {	/* ARM_VST4d8_UPD, ARM_INS_VST4: vst4${p}.8	\{$vd, $src2, $src3, $src4\}, $rn$rm */
4996 {	/* ARM_VST4q16, ARM_INS_VST4: vst4${p}.16	\{$vd, $src2, $src3, $src4\}, $rn */
4999 {	/* ARM_VST4q16_UPD, ARM_INS_VST4: vst4${p}.16	\{$vd, $src2, $src3, $src4\}, $rn$rm */
5002 {	/* ARM_VST4q32, ARM_INS_VST4: vst4${p}.32	\{$vd, $src2, $src3, $src4\}, $rn */
5005 {	/* ARM_VST4q32_UPD, ARM_INS_VST4: vst4${p}.32	\{$vd, $src2, $src3, $src4\}, $rn$rm */
5008 {	/* ARM_VST4q8, ARM_INS_VST4: vst4${p}.8	\{$vd, $src2, $src3, $src4\}, $rn */
5011 {	/* ARM_VST4q8_UPD, ARM_INS_VST4: vst4${p}.8	\{$vd, $src2, $src3, $src4\}, $rn$rm */
5041 {	/* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn${p}.i64	$vd, $vn, $vm */
5044 {	/* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn${p}.i32	$vd, $vn, $vm */
5047 {	/* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn${p}.i16	$vd, $vn, $vm */
5050 {	/* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl${p}.s32	$vd, $vn, $vm */
5053 {	/* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl${p}.s16	$vd, $vn, $vm */
5056 {	/* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl${p}.s8	$vd, $vn, $vm */
5059 {	/* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl${p}.u32	$vd, $vn, $vm */
5062 {	/* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl${p}.u16	$vd, $vn, $vm */
5065 {	/* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl${p}.u8	$vd, $vn, $vm */
5071 {	/* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw${p}.s32	$vd, $vn, $vm */
5074 {	/* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw${p}.s16	$vd, $vn, $vm */
5077 {	/* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw${p}.s8	$vd, $vn, $vm */
5080 {	/* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw${p}.u32	$vd, $vn, $vm */
5083 {	/* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw${p}.u16	$vd, $vn, $vm */
5086 {	/* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw${p}.u8	$vd, $vn, $vm */
5089 {	/* ARM_VSUBfd, ARM_INS_VSUB: vsub${p}.f32	$vd, $vn, $vm */
5092 {	/* ARM_VSUBfq, ARM_INS_VSUB: vsub${p}.f32	$vd, $vn, $vm */
5095 {	/* ARM_VSUBv16i8, ARM_INS_VSUB: vsub${p}.i8	$vd, $vn, $vm */
5098 {	/* ARM_VSUBv1i64, ARM_INS_VSUB: vsub${p}.i64	$vd, $vn, $vm */
5101 {	/* ARM_VSUBv2i32, ARM_INS_VSUB: vsub${p}.i32	$vd, $vn, $vm */
5104 {	/* ARM_VSUBv2i64, ARM_INS_VSUB: vsub${p}.i64	$vd, $vn, $vm */
5107 {	/* ARM_VSUBv4i16, ARM_INS_VSUB: vsub${p}.i16	$vd, $vn, $vm */
5110 {	/* ARM_VSUBv4i32, ARM_INS_VSUB: vsub${p}.i32	$vd, $vn, $vm */
5113 {	/* ARM_VSUBv8i16, ARM_INS_VSUB: vsub${p}.i16	$vd, $vn, $vm */
5116 {	/* ARM_VSUBv8i8, ARM_INS_VSUB: vsub${p}.i8	$vd, $vn, $vm */
5119 {	/* ARM_VSWPd, ARM_INS_VSWP: vswp${p}	$vd, $vm */
5122 {	/* ARM_VSWPq, ARM_INS_VSWP: vswp${p}	$vd, $vm */
5125 {	/* ARM_VTBL1, ARM_INS_VTBL: vtbl${p}.8	$vd, $vn, $vm */
5128 {	/* ARM_VTBL2, ARM_INS_VTBL: vtbl${p}.8	$vd, $vn, $vm */
5131 {	/* ARM_VTBL3, ARM_INS_VTBL: vtbl${p}.8	$vd, $vn, $vm */
5134 {	/* ARM_VTBL4, ARM_INS_VTBL: vtbl${p}.8	$vd, $vn, $vm */
5137 {	/* ARM_VTBX1, ARM_INS_VTBX: vtbx${p}.8	$vd, $vn, $vm */
5140 {	/* ARM_VTBX2, ARM_INS_VTBX: vtbx${p}.8	$vd, $vn, $vm */
5143 {	/* ARM_VTBX3, ARM_INS_VTBX: vtbx${p}.8	$vd, $vn, $vm */
5146 {	/* ARM_VTBX4, ARM_INS_VTBX: vtbx${p}.8	$vd, $vn, $vm */
5197 {	/* ARM_VTRNd16, ARM_INS_VTRN: vtrn${p}.16	$vd, $vm */
5200 {	/* ARM_VTRNd32, ARM_INS_VTRN: vtrn${p}.32	$vd, $vm */
5203 {	/* ARM_VTRNd8, ARM_INS_VTRN: vtrn${p}.8	$vd, $vm */
5206 {	/* ARM_VTRNq16, ARM_INS_VTRN: vtrn${p}.16	$vd, $vm */
5209 {	/* ARM_VTRNq32, ARM_INS_VTRN: vtrn${p}.32	$vd, $vm */
5212 {	/* ARM_VTRNq8, ARM_INS_VTRN: vtrn${p}.8	$vd, $vm */
5215 {	/* ARM_VTSTv16i8, ARM_INS_VTST: vtst${p}.8	$vd, $vn, $vm */
5218 {	/* ARM_VTSTv2i32, ARM_INS_VTST: vtst${p}.32	$vd, $vn, $vm */
5221 {	/* ARM_VTSTv4i16, ARM_INS_VTST: vtst${p}.16	$vd, $vn, $vm */
5224 {	/* ARM_VTSTv4i32, ARM_INS_VTST: vtst${p}.32	$vd, $vn, $vm */
5227 {	/* ARM_VTSTv8i16, ARM_INS_VTST: vtst${p}.16	$vd, $vn, $vm */
5230 {	/* ARM_VTSTv8i8, ARM_INS_VTST: vtst${p}.8	$vd, $vn, $vm */
5251 {	/* ARM_VUZPd16, ARM_INS_VUZP: vuzp${p}.16	$vd, $vm */
5254 {	/* ARM_VUZPd8, ARM_INS_VUZP: vuzp${p}.8	$vd, $vm */
5257 {	/* ARM_VUZPq16, ARM_INS_VUZP: vuzp${p}.16	$vd, $vm */
5260 {	/* ARM_VUZPq32, ARM_INS_VUZP: vuzp${p}.32	$vd, $vm */
5263 {	/* ARM_VUZPq8, ARM_INS_VUZP: vuzp${p}.8	$vd, $vm */
5266 {	/* ARM_VZIPd16, ARM_INS_VZIP: vzip${p}.16	$vd, $vm */
5269 {	/* ARM_VZIPd8, ARM_INS_VZIP: vzip${p}.8	$vd, $vm */
5272 {	/* ARM_VZIPq16, ARM_INS_VZIP: vzip${p}.16	$vd, $vm */
5275 {	/* ARM_VZIPq32, ARM_INS_VZIP: vzip${p}.32	$vd, $vm */
5278 {	/* ARM_VZIPq8, ARM_INS_VZIP: vzip${p}.8	$vd, $vm */