25 		add_str(&result, " ; op_count: %u", arm64->op_count);  in get_detail_arm64()
33 				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));  in get_detail_arm64()
36 				add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);  in get_detail_arm64()
41 				add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);  in get_detail_arm64()
43 				add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);  in get_detail_arm64()
47 				add_str(&result, " ; operands[%u].type: MEM", i);  in get_detail_arm64()
49 					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));  in get_detail_arm64()
51 …			add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));  in get_detail_arm64()
53 					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);  in get_detail_arm64()
57 				add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm);  in get_detail_arm64()
60 				add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg);  in get_detail_arm64()
63 				add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg);  in get_detail_arm64()
66 				add_str(&result, " ; operands[%u].type: PSTATE = 0x%x", i, op->pstate);  in get_detail_arm64()
69 				add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys);  in get_detail_arm64()
72 				add_str(&result, " ; operands[%u].type: PREFETCH = 0x%x", i, op->prefetch);  in get_detail_arm64()
75 				add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);  in get_detail_arm64()
84 				add_str(&result, " ; operands[%u].access: READ", i);  in get_detail_arm64()
87 				add_str(&result, " ; operands[%u].access: WRITE", i);  in get_detail_arm64()
90 				add_str(&result, " ; operands[%u].access: READ | WRITE", i);  in get_detail_arm64()
95 			add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value);  in get_detail_arm64()
98 			add_str(&result, " ; Ext: %u", op->ext);  in get_detail_arm64()
101 			add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas);  in get_detail_arm64()
104 			add_str(&result, " ; Vector Element Size Specifier: %u", op->vess);  in get_detail_arm64()
107 			add_str(&result, " ; Vector Index: %u", op->vector_index);  in get_detail_arm64()
111 		add_str(&result, " ; Update-flags: True");  in get_detail_arm64()
114 		add_str(&result, " ; Write-back: True");  in get_detail_arm64()
117 		add_str(&result, " ; Code-condition: %u", arm64->cc);  in get_detail_arm64()
121 			add_str(&result, " ; Registers read:");  in get_detail_arm64()
123 				add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));  in get_detail_arm64()
128 			add_str(&result, " ; Registers modified:");  in get_detail_arm64()
130 				add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));  in get_detail_arm64()