194     writable_bits: [u32; NUM_CONFIGURATION_REGISTERS], // writable bits for each register.  field
298         let mut writable_bits = [0u32; NUM_CONFIGURATION_REGISTERS];  in new()  localVariable
301         writable_bits[1] = 0x0000_ffff; // Status (r/o), command (r/w)  in new()
311         writable_bits[3] = 0x0000_00ff; // Cacheline size (r/w)  in new()
315                 writable_bits[15] = 0x0000_00ff; // Interrupt line (r/w)  in new()
319                 writable_bits[9] = 0xfff0_fff0; // Memory base and limit  in new()
320                 writable_bits[15] = 0xffff_00ff; // Bridge control (r/w), interrupt line (r/w)  in new()
327             writable_bits,  in new()
362             *r = (*r & !self.writable_bits[reg_idx]) | (value & self.writable_bits[reg_idx]);  in write_dword()
381             let writable_mask = self.writable_bits[reg_idx];  in write_word()
402                 self.writable_bits[reg_idx]  in write_byte_internal()
470                 self.writable_bits[bar_idx + 1] = !((config.size - 1) >> 32) as u32;  in add_pci_bar()
490         self.writable_bits[bar_idx] = !(config.size - 1) as u32;  in add_pci_bar()
830         assert_eq!(cfg.writable_bits[BAR0_REG + 1], 0xFFFFFFFF);  in add_pci_bar_mem_64bit()
831         assert_eq!(cfg.writable_bits[BAR0_REG + 0], 0xFFFFFFF0);  in add_pci_bar_mem_64bit()
877         assert_eq!(cfg.writable_bits[BAR0_REG], 0xFFFFFFF0);  in add_pci_bar_mem_32bit()
920         assert_eq!(cfg.writable_bits[BAR0_REG], 0xFFFFFFFC);  in add_pci_bar_io()