Lines Matching full:reg
8 #define REG(_reg, _name, _val) \ macro
33 static void dsa_mv88e6161(int reg, u16 val) in dsa_mv88e6161() argument
35 switch (reg) { in dsa_mv88e6161()
37 REG(reg, "Port Status", val); in dsa_mv88e6161()
56 REG(reg, "PCS Control", val); in dsa_mv88e6161()
70 REG(reg, "Jamming Control", val); in dsa_mv88e6161()
73 REG(reg, "Switch Identifier", val); in dsa_mv88e6161()
76 REG(reg, "Port Control", val); in dsa_mv88e6161()
113 REG(reg, "Port Control 1", val); in dsa_mv88e6161()
120 REG(reg, "Port Base VLAN Map (Header)", val); in dsa_mv88e6161()
125 REG(reg, "Default VLAN ID & Priority", val); in dsa_mv88e6161()
131 REG(reg, "Port Control 2", val); in dsa_mv88e6161()
151 REG(reg, "Egress Rate Control", val); in dsa_mv88e6161()
154 REG(reg, "Egress Rate Control 2", val); in dsa_mv88e6161()
157 REG(reg, "Port Association Vector", val); in dsa_mv88e6161()
160 REG(reg, "Port ATU Control", val); in dsa_mv88e6161()
163 REG(reg, "Priority Override", val); in dsa_mv88e6161()
166 REG(reg, "PortEType", val); in dsa_mv88e6161()
169 REG(reg, "InDiscardsLo Frame Counter", val); in dsa_mv88e6161()
172 REG(reg, "InDiscardsHi Frame Counter", val); in dsa_mv88e6161()
175 REG(reg, "InFiltered Frame Counter", val); in dsa_mv88e6161()
178 REG(reg, "OutFiltered Frame Counter", val); in dsa_mv88e6161()
181 REG(reg, "Tag Remap 0-3", val); in dsa_mv88e6161()
184 REG(reg, "Tag Remap 4-7", val); in dsa_mv88e6161()
187 REG(reg, "Queue Counters", val); in dsa_mv88e6161()
190 REG(reg, "Reserved", val); in dsa_mv88e6161()
195 static void dsa_mv88e6185(int reg, u16 val) in dsa_mv88e6185() argument
197 switch (reg) { in dsa_mv88e6185()
199 REG(reg, "Port Status", val); in dsa_mv88e6185()
202 REG(reg, "PCS Control", val); in dsa_mv88e6185()
205 REG(reg, "Switch Identifier", val); in dsa_mv88e6185()
208 REG(reg, "Port Control", val); in dsa_mv88e6185()
211 REG(reg, "Port Control 1", val); in dsa_mv88e6185()
214 REG(reg, "Port Base VLAN Map (Header)", val); in dsa_mv88e6185()
217 REG(reg, "Default VLAN ID & Priority", val); in dsa_mv88e6185()
220 REG(reg, "Port Control 2", val); in dsa_mv88e6185()
223 REG(reg, "Rate Control", val); in dsa_mv88e6185()
226 REG(reg, "Rate Control 2", val); in dsa_mv88e6185()
229 REG(reg, "Port Association Vector", val); in dsa_mv88e6185()
232 REG(reg, "InDiscardsLo Frame Counter", val); in dsa_mv88e6185()
235 REG(reg, "InDiscardsHi Frame Counter", val); in dsa_mv88e6185()
238 REG(reg, "InFiltered Frame Counter", val); in dsa_mv88e6185()
241 REG(reg, "OutFiltered Frame Counter", val); in dsa_mv88e6185()
244 REG(reg, "Tag Remap 0-3", val); in dsa_mv88e6185()
247 REG(reg, "Tag Remap 4-7", val); in dsa_mv88e6185()
250 REG(reg, "Reserved", val); in dsa_mv88e6185()
255 static void dsa_mv88e6352(int reg, u16 val) in dsa_mv88e6352() argument
257 switch (reg) { in dsa_mv88e6352()
259 REG(reg, "Port Status", val); in dsa_mv88e6352()
276 REG(reg, "Physical Control", val); in dsa_mv88e6352()
293 REG(reg, "Jamming Control", val); in dsa_mv88e6352()
296 REG(reg, "Switch Identifier", val); in dsa_mv88e6352()
299 REG(reg, "Port Control", val); in dsa_mv88e6352()
336 REG(reg, "Port Control 1", val); in dsa_mv88e6352()
343 REG(reg, "Port Base VLAN Map (Header)", val); in dsa_mv88e6352()
348 REG(reg, "Default VLAN ID & Priority", val); in dsa_mv88e6352()
354 REG(reg, "Port Control 2", val); in dsa_mv88e6352()
376 REG(reg, "Egress Rate Control", val); in dsa_mv88e6352()
379 REG(reg, "Egress Rate Control 2", val); in dsa_mv88e6352()
382 REG(reg, "Port Association Vector", val); in dsa_mv88e6352()
385 REG(reg, "Port ATU Control", val); in dsa_mv88e6352()
388 REG(reg, "Override", val); in dsa_mv88e6352()
391 REG(reg, "Policy Control", val); in dsa_mv88e6352()
394 REG(reg, "Port Ether Type", val); in dsa_mv88e6352()
397 REG(reg, "InDiscardsLo Frame Counter", val); in dsa_mv88e6352()
400 REG(reg, "InDiscardsHi Frame Counter", val); in dsa_mv88e6352()
403 REG(reg, "InFiltered/TcamCtr Frame Counter", val); in dsa_mv88e6352()
406 REG(reg, "Rx Frame Counter", val); in dsa_mv88e6352()
409 REG(reg, "LED Control", val); in dsa_mv88e6352()
412 REG(reg, "Tag Remap 0-3", val); in dsa_mv88e6352()
415 REG(reg, "Tag Remap 4-7", val); in dsa_mv88e6352()
418 REG(reg, "Queue Counters", val); in dsa_mv88e6352()
421 REG(reg, "Reserved", val); in dsa_mv88e6352()
426 static void dsa_mv88e6390(int reg, u16 val) in dsa_mv88e6390() argument
428 switch (reg) { in dsa_mv88e6390()
430 REG(reg, "Port Status", val); in dsa_mv88e6390()
448 REG(reg, "Physical Control", val); in dsa_mv88e6390()
467 REG(reg, "Flow Control", val); in dsa_mv88e6390()
470 REG(reg, "Switch Identifier", val); in dsa_mv88e6390()
473 REG(reg, "Port Control", val); in dsa_mv88e6390()
510 REG(reg, "Port Control 1", val); in dsa_mv88e6390()
518 REG(reg, "Port Base VLAN Map (Header)", val); in dsa_mv88e6390()
524 REG(reg, "Default VLAN ID & Priority", val); in dsa_mv88e6390()
530 REG(reg, "Port Control 2", val); in dsa_mv88e6390()
553 REG(reg, "Egress Rate Control", val); in dsa_mv88e6390()
556 REG(reg, "Egress Rate Control 2", val); in dsa_mv88e6390()
559 REG(reg, "Port Association Vector", val); in dsa_mv88e6390()
562 REG(reg, "Port ATU Control", val); in dsa_mv88e6390()
565 REG(reg, "Override", val); in dsa_mv88e6390()
568 REG(reg, "Policy Control", val); in dsa_mv88e6390()
571 REG(reg, "Port Ether Type", val); in dsa_mv88e6390()
574 REG(reg, "LED Control", val); in dsa_mv88e6390()
577 REG(reg, "IP Priority Mapping Table", val); in dsa_mv88e6390()
580 REG(reg, "IEEE Priority Mapping Table", val); in dsa_mv88e6390()
583 REG(reg, "Port Control 3", val); in dsa_mv88e6390()
586 REG(reg, "Queue Counters", val); in dsa_mv88e6390()
589 REG(reg, "Queue Control", val); in dsa_mv88e6390()
592 REG(reg, "Cut Through Control", val); in dsa_mv88e6390()
595 REG(reg, "Debug Counters", val); in dsa_mv88e6390()
598 REG(reg, "Reserved", val); in dsa_mv88e6390()
604 void (*dump)(int reg, u16 val);
668 REG(i, "", data[i]); in dsa_mv88e6xxx_dump_regs()
675 #undef REG