Lines Matching full:reg
9 u32 *reg = (u32 *)regs->data; in et131x_dump_regs() local
15 fprintf(stdout, "0x0, Basic Control Reg = 0x%04X\n", *reg++); in et131x_dump_regs()
16 fprintf(stdout, "0x1, Basic Status Reg = 0x%04X\n", *reg++); in et131x_dump_regs()
17 fprintf(stdout, "0x2, PHY identifier 1 = 0x%04X\n", *reg++); in et131x_dump_regs()
18 fprintf(stdout, "0x3, PHY identifier 2 = 0x%04X\n", *reg++); in et131x_dump_regs()
19 fprintf(stdout, "0x4, Auto Neg Advertisement = 0x%04X\n", *reg++); in et131x_dump_regs()
20 fprintf(stdout, "0x5, Auto Neg L Partner Ability = 0x%04X\n", *reg++); in et131x_dump_regs()
21 fprintf(stdout, "0x6, Auto Neg Expansion = 0x%04X\n", *reg++); in et131x_dump_regs()
22 fprintf(stdout, "0x7, Reserved = 0x%04X\n", *reg++); in et131x_dump_regs()
23 fprintf(stdout, "0x8, Reserved = 0x%04X\n", *reg++); in et131x_dump_regs()
24 fprintf(stdout, "0x9, 1000T Control = 0x%04X\n", *reg++); in et131x_dump_regs()
25 fprintf(stdout, "0xA, 1000T Status = 0x%04X\n", *reg++); in et131x_dump_regs()
26 fprintf(stdout, "0xB, Reserved = 0x%04X\n", *reg++); in et131x_dump_regs()
27 fprintf(stdout, "0xC, Reserved = 0x%04X\n", *reg++); in et131x_dump_regs()
28 fprintf(stdout, "0xD, MMD Access Control = 0x%04X\n", *reg++); in et131x_dump_regs()
29 fprintf(stdout, "0xE, MMD access Data = 0x%04X\n", *reg++); in et131x_dump_regs()
30 fprintf(stdout, "0xF, Extended Status = 0x%04X\n", *reg++); in et131x_dump_regs()
31 fprintf(stdout, "0x10, Phy Index = 0x%04X\n", *reg++); in et131x_dump_regs()
32 fprintf(stdout, "0x11, Phy Data = 0x%04X\n", *reg++); in et131x_dump_regs()
33 fprintf(stdout, "0x12, MPhy Control = 0x%04X\n", *reg++); in et131x_dump_regs()
34 fprintf(stdout, "0x13, Phy Loopback Control1 = 0x%04X\n", *reg++); in et131x_dump_regs()
35 fprintf(stdout, "0x14, Phy Loopback Control2 = 0x%04X\n", *reg++); in et131x_dump_regs()
36 fprintf(stdout, "0x15, Register Management = 0x%04X\n", *reg++); in et131x_dump_regs()
37 fprintf(stdout, "0x16, Phy Config = 0x%04X\n", *reg++); in et131x_dump_regs()
38 fprintf(stdout, "0x17, Phy Phy Control = 0x%04X\n", *reg++); in et131x_dump_regs()
39 fprintf(stdout, "0x18, Phy Interrupt Mask = 0x%04X\n", *reg++); in et131x_dump_regs()
40 fprintf(stdout, "0x19, Phy Interrupt Status = 0x%04X\n", *reg++); in et131x_dump_regs()
41 fprintf(stdout, "0x1A, Phy Phy Status = 0x%04X\n", *reg++); in et131x_dump_regs()
42 fprintf(stdout, "0x1B, Phy LED1 = 0x%04X\n", *reg++); in et131x_dump_regs()
43 fprintf(stdout, "0x1C, Phy LED2 = 0x%04X\n", *reg++); in et131x_dump_regs()
47 fprintf(stdout, "0x0, TXQ Start Address = 0x%04X\n", *reg++); in et131x_dump_regs()
48 fprintf(stdout, "0x1, TXQ End Address = 0x%04X\n", *reg++); in et131x_dump_regs()
49 fprintf(stdout, "0x2, RXQ Start Address = 0x%04X\n", *reg++); in et131x_dump_regs()
50 fprintf(stdout, "0x3, RXQ End Address = 0x%04X\n", *reg++); in et131x_dump_regs()
51 fprintf(stdout, "0x4, Power Management Status = 0x%04X\n", *reg++); in et131x_dump_regs()
52 fprintf(stdout, "0x5, Interrupt Status = 0x%04X\n", *reg++); in et131x_dump_regs()
53 fprintf(stdout, "0x6, Interrupt Mask = 0x%04X\n", *reg++); in et131x_dump_regs()
54 fprintf(stdout, "0x7, Int Alias Clear Mask = 0x%04X\n", *reg++); in et131x_dump_regs()
55 fprintf(stdout, "0x8, Int Status Alias = 0x%04X\n", *reg++); in et131x_dump_regs()
56 fprintf(stdout, "0x9, Software Reset = 0x%04X\n", *reg++); in et131x_dump_regs()
57 fprintf(stdout, "0xA, SLV Timer = 0x%04X\n", *reg++); in et131x_dump_regs()
58 fprintf(stdout, "0xB, MSI Config = 0x%04X\n", *reg++); in et131x_dump_regs()
59 fprintf(stdout, "0xC, Loopback = 0x%04X\n", *reg++); in et131x_dump_regs()
60 fprintf(stdout, "0xD, Watchdog Timer = 0x%04X\n", *reg++); in et131x_dump_regs()
64 fprintf(stdout, "0x0, Control Status = 0x%04X\n", *reg++); in et131x_dump_regs()
65 fprintf(stdout, "0x1, Packet Ring Base Addr (Hi) = 0x%04X\n", *reg++); in et131x_dump_regs()
66 fprintf(stdout, "0x2, Packet Ring Base Addr (Lo) = 0x%04X\n", *reg++); in et131x_dump_regs()
67 fprintf(stdout, "0x3, Packet Ring Num Descrs = 0x%04X\n", *reg++); in et131x_dump_regs()
68 fprintf(stdout, "0x4, TX Queue Write Address = 0x%04X\n", *reg++); in et131x_dump_regs()
69 fprintf(stdout, "0x5, TX Queue Write Address Ext = 0x%04X\n", *reg++); in et131x_dump_regs()
70 fprintf(stdout, "0x6, TX Queue Read Address = 0x%04X\n", *reg++); in et131x_dump_regs()
71 fprintf(stdout, "0x7, Status Writeback Addr (Hi) = 0x%04X\n", *reg++); in et131x_dump_regs()
72 fprintf(stdout, "0x8, Status Writeback Addr (Lo) = 0x%04X\n", *reg++); in et131x_dump_regs()
73 fprintf(stdout, "0x9, Service Request = 0x%04X\n", *reg++); in et131x_dump_regs()
74 fprintf(stdout, "0xA, Service Complete = 0x%04X\n", *reg++); in et131x_dump_regs()
75 fprintf(stdout, "0xB, Cache Read Index = 0x%04X\n", *reg++); in et131x_dump_regs()
76 fprintf(stdout, "0xC, Cache Write Index = 0x%04X\n", *reg++); in et131x_dump_regs()
77 fprintf(stdout, "0xD, TXDMA Error = 0x%04X\n", *reg++); in et131x_dump_regs()
78 fprintf(stdout, "0xE, Descriptor Abort Count = 0x%04X\n", *reg++); in et131x_dump_regs()
79 fprintf(stdout, "0xF, Payload Abort Count = 0x%04X\n", *reg++); in et131x_dump_regs()
80 fprintf(stdout, "0x10, Writeback Abort Count = 0x%04X\n", *reg++); in et131x_dump_regs()
81 fprintf(stdout, "0x11, Descriptor Timeout Count = 0x%04X\n", *reg++); in et131x_dump_regs()
82 fprintf(stdout, "0x12, Payload Timeout Count = 0x%04X\n", *reg++); in et131x_dump_regs()
83 fprintf(stdout, "0x13, Writeback Timeout Count = 0x%04X\n", *reg++); in et131x_dump_regs()
84 fprintf(stdout, "0x14, Descriptor Error Count = 0x%04X\n", *reg++); in et131x_dump_regs()
85 fprintf(stdout, "0x15, Payload Error Count = 0x%04X\n", *reg++); in et131x_dump_regs()
86 fprintf(stdout, "0x16, Writeback Error Count = 0x%04X\n", *reg++); in et131x_dump_regs()
87 fprintf(stdout, "0x17, Dropped TLP Count = 0x%04X\n", *reg++); in et131x_dump_regs()
88 fprintf(stdout, "0x18, New service Complete = 0x%04X\n", *reg++); in et131x_dump_regs()
89 fprintf(stdout, "0x1A, Ethernet Packet Count = 0x%04X\n", *reg++); in et131x_dump_regs()
93 fprintf(stdout, "0x0, Control Status = 0x%04X\n", *reg++); in et131x_dump_regs()
94 fprintf(stdout, "0x1, Writeback Addr (Hi) = 0x%04X\n", *reg++); in et131x_dump_regs()
95 fprintf(stdout, "0x2, Writeback Addr (Lo) = 0x%04X\n", *reg++); in et131x_dump_regs()
96 fprintf(stdout, "0x3, Num Packets Done = 0x%04X\n", *reg++); in et131x_dump_regs()
97 fprintf(stdout, "0x4, Max Packet Time = 0x%04X\n", *reg++); in et131x_dump_regs()
98 fprintf(stdout, "0x5, RX Queue Read Addr = 0x%04X\n", *reg++); in et131x_dump_regs()
99 fprintf(stdout, "0x6, RX Queue Read Address Ext = 0x%04X\n", *reg++); in et131x_dump_regs()
100 fprintf(stdout, "0x7, RX Queue Write Addr = 0x%04X\n", *reg++); in et131x_dump_regs()
101 fprintf(stdout, "0x8, Packet Ring Base Addr (Hi) = 0x%04X\n", *reg++); in et131x_dump_regs()
102 fprintf(stdout, "0x9, Packet Ring Base Addr (Lo) = 0x%04X\n", *reg++); in et131x_dump_regs()
103 fprintf(stdout, "0xA, Packet Ring Num Descrs = 0x%04X\n", *reg++); in et131x_dump_regs()
104 fprintf(stdout, "0xE, Packet Ring Avail Offset = 0x%04X\n", *reg++); in et131x_dump_regs()
105 fprintf(stdout, "0xF, Packet Ring Full Offset = 0x%04X\n", *reg++); in et131x_dump_regs()
106 fprintf(stdout, "0x10, Packet Ring Access Index = 0x%04X\n", *reg++); in et131x_dump_regs()
107 fprintf(stdout, "0x11, Packet Ring Min Descrip = 0x%04X\n", *reg++); in et131x_dump_regs()
108 fprintf(stdout, "0x12, FBR0 Address (Lo) = 0x%04X\n", *reg++); in et131x_dump_regs()
109 fprintf(stdout, "0x13, FBR0 Address (Hi) = 0x%04X\n", *reg++); in et131x_dump_regs()
110 fprintf(stdout, "0x14, FBR0 Num Descriptors = 0x%04X\n", *reg++); in et131x_dump_regs()
111 fprintf(stdout, "0x15, FBR0 Available Offset = 0x%04X\n", *reg++); in et131x_dump_regs()
112 fprintf(stdout, "0x16, FBR0 Full Offset = 0x%04X\n", *reg++); in et131x_dump_regs()
113 fprintf(stdout, "0x17, FBR0 Read Index = 0x%04X\n", *reg++); in et131x_dump_regs()
114 fprintf(stdout, "0x18, FBR0 Minimum Descriptors = 0x%04X\n", *reg++); in et131x_dump_regs()
115 fprintf(stdout, "0x19, FBR1 Address (Lo) = 0x%04X\n", *reg++); in et131x_dump_regs()
116 fprintf(stdout, "0x1A, FBR1 Address (Hi) = 0x%04X\n", *reg++); in et131x_dump_regs()
117 fprintf(stdout, "0x1B, FBR1 Num Descriptors = 0x%04X\n", *reg++); in et131x_dump_regs()
118 fprintf(stdout, "0x1C, FBR1 Available Offset = 0x%04X\n", *reg++); in et131x_dump_regs()
119 fprintf(stdout, "0x1D, FBR1 Full Offset = 0x%04X\n", *reg++); in et131x_dump_regs()
120 fprintf(stdout, "0x1E, FBR1 Read Index = 0x%04X\n", *reg++); in et131x_dump_regs()
121 fprintf(stdout, "0x1F, FBR1 Minimum Descriptors = 0x%04X\n", *reg++); in et131x_dump_regs()