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38 #define INTEL_VGA_DEVICE(id, info) {		\  argument
42 (unsigned long) info }
44 #define INTEL_QUANTA_VGA_DEVICE(info) { \ argument
48 (unsigned long) info }
50 #define INTEL_I810_IDS(info) \ argument
51 INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
52 INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
53 INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
55 #define INTEL_I815_IDS(info) \ argument
56 INTEL_VGA_DEVICE(0x1132, info) /* I815*/
58 #define INTEL_I830_IDS(info) \ argument
59 INTEL_VGA_DEVICE(0x3577, info)
61 #define INTEL_I845G_IDS(info) \ argument
62 INTEL_VGA_DEVICE(0x2562, info)
64 #define INTEL_I85X_IDS(info) \ argument
65 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
66 INTEL_VGA_DEVICE(0x358e, info)
68 #define INTEL_I865G_IDS(info) \ argument
69 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
71 #define INTEL_I915G_IDS(info) \ argument
72 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
73 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
75 #define INTEL_I915GM_IDS(info) \ argument
76 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
78 #define INTEL_I945G_IDS(info) \ argument
79 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
81 #define INTEL_I945GM_IDS(info) \ argument
82 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
83 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
85 #define INTEL_I965G_IDS(info) \ argument
86 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
87 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
88 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
89 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
91 #define INTEL_G33_IDS(info) \ argument
92 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
93 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
94 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
96 #define INTEL_I965GM_IDS(info) \ argument
97 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
98 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
100 #define INTEL_GM45_IDS(info) \ argument
101 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
103 #define INTEL_G45_IDS(info) \ argument
104 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
105 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
106 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
107 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
108 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
109 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
111 #define INTEL_PINEVIEW_G_IDS(info) \ argument
112 INTEL_VGA_DEVICE(0xa001, info)
114 #define INTEL_PINEVIEW_M_IDS(info) \ argument
115 INTEL_VGA_DEVICE(0xa011, info)
117 #define INTEL_IRONLAKE_D_IDS(info) \ argument
118 INTEL_VGA_DEVICE(0x0042, info)
120 #define INTEL_IRONLAKE_M_IDS(info) \ argument
121 INTEL_VGA_DEVICE(0x0046, info)
123 #define INTEL_SNB_D_GT1_IDS(info) \ argument
124 INTEL_VGA_DEVICE(0x0102, info), \
125 INTEL_VGA_DEVICE(0x010A, info)
127 #define INTEL_SNB_D_GT2_IDS(info) \ argument
128 INTEL_VGA_DEVICE(0x0112, info), \
129 INTEL_VGA_DEVICE(0x0122, info)
131 #define INTEL_SNB_D_IDS(info) \ argument
132 INTEL_SNB_D_GT1_IDS(info), \
133 INTEL_SNB_D_GT2_IDS(info)
135 #define INTEL_SNB_M_GT1_IDS(info) \ argument
136 INTEL_VGA_DEVICE(0x0106, info)
138 #define INTEL_SNB_M_GT2_IDS(info) \ argument
139 INTEL_VGA_DEVICE(0x0116, info), \
140 INTEL_VGA_DEVICE(0x0126, info)
142 #define INTEL_SNB_M_IDS(info) \ argument
143 INTEL_SNB_M_GT1_IDS(info), \
144 INTEL_SNB_M_GT2_IDS(info)
146 #define INTEL_IVB_M_GT1_IDS(info) \ argument
147 INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
149 #define INTEL_IVB_M_GT2_IDS(info) \ argument
150 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
152 #define INTEL_IVB_M_IDS(info) \ argument
153 INTEL_IVB_M_GT1_IDS(info), \
154 INTEL_IVB_M_GT2_IDS(info)
156 #define INTEL_IVB_D_GT1_IDS(info) \ argument
157 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
158 INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
160 #define INTEL_IVB_D_GT2_IDS(info) \ argument
161 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
162 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
164 #define INTEL_IVB_D_IDS(info) \ argument
165 INTEL_IVB_D_GT1_IDS(info), \
166 INTEL_IVB_D_GT2_IDS(info)
168 #define INTEL_IVB_Q_IDS(info) \ argument
169 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
171 #define INTEL_HSW_ULT_GT1_IDS(info) \ argument
172 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
173 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
174 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
175 INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
177 #define INTEL_HSW_ULX_GT1_IDS(info) \ argument
178 INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
180 #define INTEL_HSW_GT1_IDS(info) \ argument
181 INTEL_HSW_ULT_GT1_IDS(info), \
182 INTEL_HSW_ULX_GT1_IDS(info), \
183 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
184 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
185 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
186 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
187 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
188 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
189 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
190 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
191 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
192 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
193 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
194 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
195 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
196 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
197 INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
199 #define INTEL_HSW_ULT_GT2_IDS(info) \ argument
200 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
201 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
202 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
203 INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
205 #define INTEL_HSW_ULX_GT2_IDS(info) \ argument
206 INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
208 #define INTEL_HSW_GT2_IDS(info) \ argument
209 INTEL_HSW_ULT_GT2_IDS(info), \
210 INTEL_HSW_ULX_GT2_IDS(info), \
211 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
212 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
213 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
214 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
215 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
216 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
217 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
218 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
219 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
220 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
221 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
222 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
223 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
224 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
225 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
226 INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
228 #define INTEL_HSW_ULT_GT3_IDS(info) \ argument
229 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
230 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
231 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
232 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
233 INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
235 #define INTEL_HSW_GT3_IDS(info) \ argument
236 INTEL_HSW_ULT_GT3_IDS(info), \
237 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
238 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
239 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
240 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
241 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
242 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
243 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
244 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
245 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
246 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
247 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
248 INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
249 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
250 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
252 #define INTEL_HSW_IDS(info) \ argument
253 INTEL_HSW_GT1_IDS(info), \
254 INTEL_HSW_GT2_IDS(info), \
255 INTEL_HSW_GT3_IDS(info)
257 #define INTEL_VLV_IDS(info) \ argument
258 INTEL_VGA_DEVICE(0x0f30, info), \
259 INTEL_VGA_DEVICE(0x0f31, info), \
260 INTEL_VGA_DEVICE(0x0f32, info), \
261 INTEL_VGA_DEVICE(0x0f33, info), \
262 INTEL_VGA_DEVICE(0x0157, info), \
263 INTEL_VGA_DEVICE(0x0155, info)
265 #define INTEL_BDW_ULT_GT1_IDS(info) \ argument
266 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
267 INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
269 #define INTEL_BDW_ULX_GT1_IDS(info) \ argument
270 INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
272 #define INTEL_BDW_GT1_IDS(info) \ argument
273 INTEL_BDW_ULT_GT1_IDS(info), \
274 INTEL_BDW_ULX_GT1_IDS(info), \
275 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
276 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
277 INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
279 #define INTEL_BDW_ULT_GT2_IDS(info) \ argument
280 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
281 INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
283 #define INTEL_BDW_ULX_GT2_IDS(info) \ argument
284 INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
286 #define INTEL_BDW_GT2_IDS(info) \ argument
287 INTEL_BDW_ULT_GT2_IDS(info), \
288 INTEL_BDW_ULX_GT2_IDS(info), \
289 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
290 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
291 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
293 #define INTEL_BDW_ULT_GT3_IDS(info) \ argument
294 INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
295 INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
297 #define INTEL_BDW_ULX_GT3_IDS(info) \ argument
298 INTEL_VGA_DEVICE(0x162E, info) /* ULX */
300 #define INTEL_BDW_GT3_IDS(info) \ argument
301 INTEL_BDW_ULT_GT3_IDS(info), \
302 INTEL_BDW_ULX_GT3_IDS(info), \
303 INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
304 INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
305 INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
307 #define INTEL_BDW_ULT_RSVD_IDS(info) \ argument
308 INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
309 INTEL_VGA_DEVICE(0x163B, info) /* Iris */
311 #define INTEL_BDW_ULX_RSVD_IDS(info) \ argument
312 INTEL_VGA_DEVICE(0x163E, info) /* ULX */
314 #define INTEL_BDW_RSVD_IDS(info) \ argument
315 INTEL_BDW_ULT_RSVD_IDS(info), \
316 INTEL_BDW_ULX_RSVD_IDS(info), \
317 INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
318 INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
319 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
321 #define INTEL_BDW_IDS(info) \ argument
322 INTEL_BDW_GT1_IDS(info), \
323 INTEL_BDW_GT2_IDS(info), \
324 INTEL_BDW_GT3_IDS(info), \
325 INTEL_BDW_RSVD_IDS(info)
327 #define INTEL_CHV_IDS(info) \ argument
328 INTEL_VGA_DEVICE(0x22b0, info), \
329 INTEL_VGA_DEVICE(0x22b1, info), \
330 INTEL_VGA_DEVICE(0x22b2, info), \
331 INTEL_VGA_DEVICE(0x22b3, info)
333 #define INTEL_SKL_ULT_GT1_IDS(info) \ argument
334 INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
336 #define INTEL_SKL_ULX_GT1_IDS(info) \ argument
337 INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
339 #define INTEL_SKL_GT1_IDS(info) \ argument
340 INTEL_SKL_ULT_GT1_IDS(info), \
341 INTEL_SKL_ULX_GT1_IDS(info), \
342 INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
343 INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
344 INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
346 #define INTEL_SKL_ULT_GT2_IDS(info) \ argument
347 INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
348 INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
350 #define INTEL_SKL_ULX_GT2_IDS(info) \ argument
351 INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
353 #define INTEL_SKL_GT2_IDS(info) \ argument
354 INTEL_SKL_ULT_GT2_IDS(info), \
355 INTEL_SKL_ULX_GT2_IDS(info), \
356 INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
357 INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
358 INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
359 INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
361 #define INTEL_SKL_ULT_GT3_IDS(info) \ argument
362 INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
364 #define INTEL_SKL_GT3_IDS(info) \ argument
365 INTEL_SKL_ULT_GT3_IDS(info), \
366 INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
367 INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
368 INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
369 INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
371 #define INTEL_SKL_GT4_IDS(info) \ argument
372 INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
373 INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
374 INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
375 INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
376 INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
378 #define INTEL_SKL_IDS(info) \ argument
379 INTEL_SKL_GT1_IDS(info), \
380 INTEL_SKL_GT2_IDS(info), \
381 INTEL_SKL_GT3_IDS(info), \
382 INTEL_SKL_GT4_IDS(info)
384 #define INTEL_BXT_IDS(info) \ argument
385 INTEL_VGA_DEVICE(0x0A84, info), \
386 INTEL_VGA_DEVICE(0x1A84, info), \
387 INTEL_VGA_DEVICE(0x1A85, info), \
388 INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
389 INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
391 #define INTEL_GLK_IDS(info) \ argument
392 INTEL_VGA_DEVICE(0x3184, info), \
393 INTEL_VGA_DEVICE(0x3185, info)
395 #define INTEL_KBL_ULT_GT1_IDS(info) \ argument
396 INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
397 INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
399 #define INTEL_KBL_ULX_GT1_IDS(info) \ argument
400 INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
401 INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
403 #define INTEL_KBL_GT1_IDS(info) \ argument
404 INTEL_KBL_ULT_GT1_IDS(info), \
405 INTEL_KBL_ULX_GT1_IDS(info), \
406 INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
407 INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
408 INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
409 INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
411 #define INTEL_KBL_ULT_GT2_IDS(info) \ argument
412 INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
413 INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
415 #define INTEL_KBL_ULX_GT2_IDS(info) \ argument
416 INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
418 #define INTEL_KBL_GT2_IDS(info) \ argument
419 INTEL_KBL_ULT_GT2_IDS(info), \
420 INTEL_KBL_ULX_GT2_IDS(info), \
421 INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
422 INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
423 INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
424 INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
425 INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
427 #define INTEL_KBL_ULT_GT3_IDS(info) \ argument
428 INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
430 #define INTEL_KBL_GT3_IDS(info) \ argument
431 INTEL_KBL_ULT_GT3_IDS(info), \
432 INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
433 INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
435 #define INTEL_KBL_GT4_IDS(info) \ argument
436 INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
439 #define INTEL_AML_KBL_GT2_IDS(info) \ argument
440 INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
441 INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
444 #define INTEL_AML_CFL_GT2_IDS(info) \ argument
445 INTEL_VGA_DEVICE(0x87CA, info)
448 #define INTEL_CML_GT1_IDS(info) \ argument
449 INTEL_VGA_DEVICE(0x9B21, info), \
450 INTEL_VGA_DEVICE(0x9BAA, info), \
451 INTEL_VGA_DEVICE(0x9BAB, info), \
452 INTEL_VGA_DEVICE(0x9BAC, info), \
453 INTEL_VGA_DEVICE(0x9BA0, info), \
454 INTEL_VGA_DEVICE(0x9BA5, info), \
455 INTEL_VGA_DEVICE(0x9BA8, info), \
456 INTEL_VGA_DEVICE(0x9BA4, info), \
457 INTEL_VGA_DEVICE(0x9BA2, info)
460 #define INTEL_CML_GT2_IDS(info) \ argument
461 INTEL_VGA_DEVICE(0x9B41, info), \
462 INTEL_VGA_DEVICE(0x9BCA, info), \
463 INTEL_VGA_DEVICE(0x9BCB, info), \
464 INTEL_VGA_DEVICE(0x9BCC, info), \
465 INTEL_VGA_DEVICE(0x9BC0, info), \
466 INTEL_VGA_DEVICE(0x9BC5, info), \
467 INTEL_VGA_DEVICE(0x9BC8, info), \
468 INTEL_VGA_DEVICE(0x9BC4, info), \
469 INTEL_VGA_DEVICE(0x9BC2, info)
471 #define INTEL_KBL_IDS(info) \ argument
472 INTEL_KBL_GT1_IDS(info), \
473 INTEL_KBL_GT2_IDS(info), \
474 INTEL_KBL_GT3_IDS(info), \
475 INTEL_KBL_GT4_IDS(info), \
476 INTEL_AML_KBL_GT2_IDS(info)
479 #define INTEL_CFL_S_GT1_IDS(info) \ argument
480 INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
481 INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
482 INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
484 #define INTEL_CFL_S_GT2_IDS(info) \ argument
485 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
486 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
487 INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
488 INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
489 INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
492 #define INTEL_CFL_H_GT1_IDS(info) \ argument
493 INTEL_VGA_DEVICE(0x3E9C, info)
495 #define INTEL_CFL_H_GT2_IDS(info) \ argument
496 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
497 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
500 #define INTEL_CFL_U_GT2_IDS(info) \ argument
501 INTEL_VGA_DEVICE(0x3EA9, info)
504 #define INTEL_CFL_U_GT3_IDS(info) \ argument
505 INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
506 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
507 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
508 INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
511 #define INTEL_WHL_U_GT1_IDS(info) \ argument
512 INTEL_VGA_DEVICE(0x3EA1, info), \
513 INTEL_VGA_DEVICE(0x3EA4, info)
516 #define INTEL_WHL_U_GT2_IDS(info) \ argument
517 INTEL_VGA_DEVICE(0x3EA0, info), \
518 INTEL_VGA_DEVICE(0x3EA3, info)
521 #define INTEL_WHL_U_GT3_IDS(info) \ argument
522 INTEL_VGA_DEVICE(0x3EA2, info)
524 #define INTEL_CFL_IDS(info) \ argument
525 INTEL_CFL_S_GT1_IDS(info), \
526 INTEL_CFL_S_GT2_IDS(info), \
527 INTEL_CFL_H_GT1_IDS(info), \
528 INTEL_CFL_H_GT2_IDS(info), \
529 INTEL_CFL_U_GT2_IDS(info), \
530 INTEL_CFL_U_GT3_IDS(info), \
531 INTEL_WHL_U_GT1_IDS(info), \
532 INTEL_WHL_U_GT2_IDS(info), \
533 INTEL_WHL_U_GT3_IDS(info), \
534 INTEL_AML_CFL_GT2_IDS(info), \
535 INTEL_CML_GT1_IDS(info), \
536 INTEL_CML_GT2_IDS(info)
539 #define INTEL_CNL_PORT_F_IDS(info) \ argument
540 INTEL_VGA_DEVICE(0x5A54, info), \
541 INTEL_VGA_DEVICE(0x5A5C, info), \
542 INTEL_VGA_DEVICE(0x5A44, info), \
543 INTEL_VGA_DEVICE(0x5A4C, info)
545 #define INTEL_CNL_IDS(info) \ argument
546 INTEL_CNL_PORT_F_IDS(info), \
547 INTEL_VGA_DEVICE(0x5A51, info), \
548 INTEL_VGA_DEVICE(0x5A59, info), \
549 INTEL_VGA_DEVICE(0x5A41, info), \
550 INTEL_VGA_DEVICE(0x5A49, info), \
551 INTEL_VGA_DEVICE(0x5A52, info), \
552 INTEL_VGA_DEVICE(0x5A5A, info), \
553 INTEL_VGA_DEVICE(0x5A42, info), \
554 INTEL_VGA_DEVICE(0x5A4A, info), \
555 INTEL_VGA_DEVICE(0x5A50, info), \
556 INTEL_VGA_DEVICE(0x5A40, info)
559 #define INTEL_ICL_PORT_F_IDS(info) \ argument
560 INTEL_VGA_DEVICE(0x8A50, info), \
561 INTEL_VGA_DEVICE(0x8A5C, info), \
562 INTEL_VGA_DEVICE(0x8A59, info), \
563 INTEL_VGA_DEVICE(0x8A58, info), \
564 INTEL_VGA_DEVICE(0x8A52, info), \
565 INTEL_VGA_DEVICE(0x8A5A, info), \
566 INTEL_VGA_DEVICE(0x8A5B, info), \
567 INTEL_VGA_DEVICE(0x8A57, info), \
568 INTEL_VGA_DEVICE(0x8A56, info), \
569 INTEL_VGA_DEVICE(0x8A71, info), \
570 INTEL_VGA_DEVICE(0x8A70, info), \
571 INTEL_VGA_DEVICE(0x8A53, info), \
572 INTEL_VGA_DEVICE(0x8A54, info)
574 #define INTEL_ICL_11_IDS(info) \ argument
575 INTEL_ICL_PORT_F_IDS(info), \
576 INTEL_VGA_DEVICE(0x8A51, info), \
577 INTEL_VGA_DEVICE(0x8A5D, info)
580 #define INTEL_EHL_IDS(info) \ argument
581 INTEL_VGA_DEVICE(0x4500, info), \
582 INTEL_VGA_DEVICE(0x4571, info), \
583 INTEL_VGA_DEVICE(0x4551, info), \
584 INTEL_VGA_DEVICE(0x4541, info)
587 #define INTEL_TGL_12_IDS(info) \ argument
588 INTEL_VGA_DEVICE(0x9A49, info), \
589 INTEL_VGA_DEVICE(0x9A40, info), \
590 INTEL_VGA_DEVICE(0x9A59, info), \
591 INTEL_VGA_DEVICE(0x9A60, info), \
592 INTEL_VGA_DEVICE(0x9A68, info), \
593 INTEL_VGA_DEVICE(0x9A70, info), \
594 INTEL_VGA_DEVICE(0x9A78, info)