Lines Matching refs:surf
96 struct radeon_surface *surf);
98 struct radeon_surface *surf);
167 static void surf_minify(struct radeon_surface *surf, in surf_minify() argument
173 surflevel->npix_x = mip_minify(surf->npix_x, level); in surf_minify()
174 surflevel->npix_y = mip_minify(surf->npix_y, level); in surf_minify()
175 surflevel->npix_z = mip_minify(surf->npix_z, level); in surf_minify()
176 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in surf_minify()
177 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in surf_minify()
178 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in surf_minify()
179 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D && in surf_minify()
180 !(surf->flags & RADEON_SURF_FMASK)) { in surf_minify()
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
194 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in surf_minify()
267 struct radeon_surface *surf, in r6_surface_init_linear() argument
275 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
283 if (surf->flags & RADEON_SURF_SCANOUT) { in r6_surface_init_linear()
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
288 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_linear()
289 surf->level[i].mode = RADEON_SURF_MODE_LINEAR; in r6_surface_init_linear()
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
292 offset = surf->bo_size; in r6_surface_init_linear()
294 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_linear()
301 struct radeon_surface *surf, in r6_surface_init_linear_aligned() argument
309 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
316 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_linear_aligned()
317 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r6_surface_init_linear_aligned()
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
320 offset = surf->bo_size; in r6_surface_init_linear_aligned()
322 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_linear_aligned()
329 struct radeon_surface *surf, in r6_surface_init_1d() argument
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
341 if (surf->flags & RADEON_SURF_SCANOUT) { in r6_surface_init_1d()
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
345 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
349 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_1d()
350 surf->level[i].mode = RADEON_SURF_MODE_1D; in r6_surface_init_1d()
351 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_1d()
353 offset = surf->bo_size; in r6_surface_init_1d()
355 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_1d()
362 struct radeon_surface *surf, in r6_surface_init_2d() argument
372 (tilew * surf->bpe * surf->nsamples); in r6_surface_init_2d()
374 if (surf->flags & RADEON_SURF_FMASK) in r6_surface_init_2d()
377 if (surf->flags & RADEON_SURF_SCANOUT) { in r6_surface_init_2d()
378 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_2d()
381 surf->bo_alignment = in r6_surface_init_2d()
384 surf->nsamples * surf->bpe * 64, in r6_surface_init_2d()
385 xalign * yalign * surf->nsamples * surf->bpe); in r6_surface_init_2d()
389 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_2d()
390 surf->level[i].mode = RADEON_SURF_MODE_2D; in r6_surface_init_2d()
391 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_2d()
392 if (surf->level[i].mode == RADEON_SURF_MODE_1D) { in r6_surface_init_2d()
393 return r6_surface_init_1d(surf_man, surf, offset, i); in r6_surface_init_2d()
396 offset = surf->bo_size; in r6_surface_init_2d()
398 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_2d()
405 struct radeon_surface *surf) in r6_surface_init() argument
411 if (surf->nsamples > 1) { in r6_surface_init()
412 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in r6_surface_init()
413 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in r6_surface_init()
417 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in r6_surface_init()
419 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in r6_surface_init()
427 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in r6_surface_init()
428 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in r6_surface_init()
435 if (surf->nsamples > 1) { in r6_surface_init()
440 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in r6_surface_init()
441 surf->flags |= RADEON_SURF_SET(mode, MODE); in r6_surface_init()
445 if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) { in r6_surface_init()
450 if (surf->last_level > 14) { in r6_surface_init()
457 r = r6_surface_init_linear(surf_man, surf, 0, 0); in r6_surface_init()
460 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in r6_surface_init()
463 r = r6_surface_init_1d(surf_man, surf, 0, 0); in r6_surface_init()
466 r = r6_surface_init_2d(surf_man, surf, 0, 0); in r6_surface_init()
475 struct radeon_surface *surf) in r6_surface_best() argument
570 static void eg_surf_minify(struct radeon_surface *surf, in eg_surf_minify() argument
582 surflevel->npix_x = mip_minify(surf->npix_x, level); in eg_surf_minify()
583 surflevel->npix_y = mip_minify(surf->npix_y, level); in eg_surf_minify()
584 surflevel->npix_z = mip_minify(surf->npix_z, level); in eg_surf_minify()
585 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in eg_surf_minify()
586 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in eg_surf_minify()
587 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in eg_surf_minify()
588 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D && in eg_surf_minify()
589 !(surf->flags & RADEON_SURF_FMASK)) { in eg_surf_minify()
605 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in eg_surf_minify()
608 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in eg_surf_minify()
612 struct radeon_surface *surf, in eg_surface_init_1d() argument
622 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
626 if (surf->flags & RADEON_SURF_SCANOUT) { in eg_surface_init_1d()
632 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in eg_surface_init_1d()
640 for (i = start_level; i <= surf->last_level; i++) { in eg_surface_init_1d()
642 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset); in eg_surface_init_1d()
644 offset = surf->bo_size; in eg_surface_init_1d()
646 offset = ALIGN(offset, surf->bo_alignment); in eg_surface_init_1d()
653 struct radeon_surface *surf, in eg_surface_init_2d() argument
666 tileb = tilew * tileh * bpe * surf->nsamples; in eg_surface_init_2d()
675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
682 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in eg_surface_init_2d()
690 for (i = start_level; i <= surf->last_level; i++) { in eg_surface_init_2d()
692 eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset); in eg_surface_init_2d()
694 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i); in eg_surface_init_2d()
697 offset = surf->bo_size; in eg_surface_init_2d()
699 offset = ALIGN(offset, surf->bo_alignment); in eg_surface_init_2d()
706 struct radeon_surface *surf, in eg_surface_sanity() argument
712 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { in eg_surface_sanity()
717 if (surf->last_level > 15) { in eg_surface_sanity()
723 if (surf->nsamples > 1) { in eg_surface_sanity()
728 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in eg_surface_sanity()
729 surf->flags |= RADEON_SURF_SET(mode, MODE); in eg_surface_sanity()
734 switch (surf->tile_split) { in eg_surface_sanity()
746 switch (surf->mtilea) { in eg_surface_sanity()
756 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
760 switch (surf->bankw) { in eg_surface_sanity()
770 switch (surf->bankh) { in eg_surface_sanity()
779 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); in eg_surface_sanity()
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
789 struct radeon_surface *surf) in eg_surface_init_1d_miptrees() argument
792 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags; in eg_surface_init_1d_miptrees()
796 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_1d_miptrees()
798 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0); in eg_surface_init_1d_miptrees()
803 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
804 surf->bo_size, 0); in eg_surface_init_1d_miptrees()
805 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_1d_miptrees()
811 struct radeon_surface *surf) in eg_surface_init_2d_miptrees() argument
814 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags; in eg_surface_init_2d_miptrees()
818 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_2d_miptrees()
820 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe, in eg_surface_init_2d_miptrees()
821 surf->tile_split, 0, 0); in eg_surface_init_2d_miptrees()
826 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
827 surf->stencil_tile_split, surf->bo_size, 0); in eg_surface_init_2d_miptrees()
828 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_2d_miptrees()
834 struct radeon_surface *surf) in eg_surface_init() argument
840 if (surf->nsamples > 1) { in eg_surface_init()
841 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in eg_surface_init()
842 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in eg_surface_init()
846 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in eg_surface_init()
848 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in eg_surface_init()
856 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in eg_surface_init()
857 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in eg_surface_init()
862 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_init()
867 surf->stencil_offset = 0; in eg_surface_init()
868 surf->bo_alignment = 0; in eg_surface_init()
873 r = r6_surface_init_linear(surf_man, surf, 0, 0); in eg_surface_init()
876 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in eg_surface_init()
879 r = eg_surface_init_1d_miptrees(surf_man, surf); in eg_surface_init()
882 r = eg_surface_init_2d_miptrees(surf_man, surf); in eg_surface_init()
909 struct radeon_surface *surf) in eg_surface_best() argument
915 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in eg_surface_best()
918 surf->tile_split = 1024; in eg_surface_best()
919 surf->bankw = 1; in eg_surface_best()
920 surf->bankh = 1; in eg_surface_best()
921 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
922 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); in eg_surface_best()
923 for (; surf->bankh <= 8; surf->bankh *= 2) { in eg_surface_best()
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
928 if (surf->mtilea > 8) { in eg_surface_best()
929 surf->mtilea = 8; in eg_surface_best()
932 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_best()
943 if (surf->nsamples > 1) { in eg_surface_best()
944 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in eg_surface_best()
945 switch (surf->nsamples) { in eg_surface_best()
947 surf->tile_split = 128; in eg_surface_best()
950 surf->tile_split = 128; in eg_surface_best()
953 surf->tile_split = 256; in eg_surface_best()
956 surf->tile_split = 512; in eg_surface_best()
960 surf->nsamples, __LINE__); in eg_surface_best()
963 surf->stencil_tile_split = 64; in eg_surface_best()
968 surf->tile_split = MAX2(2 * surf->bpe * 64, 256); in eg_surface_best()
969 if (surf->tile_split > 4096) in eg_surface_best()
970 surf->tile_split = 4096; in eg_surface_best()
974 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
975 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
986 if (surf->flags & RADEON_SURF_SBUFFER) { in eg_surface_best()
990 tileb = MIN2(surf->tile_split, 64 * surf->nsamples); in eg_surface_best()
992 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); in eg_surface_best()
998 surf->bankw = 1; in eg_surface_best()
1001 surf->bankh = 4; in eg_surface_best()
1005 surf->bankh = 2; in eg_surface_best()
1008 surf->bankh = 1; in eg_surface_best()
1012 for (; surf->bankh <= 8; surf->bankh *= 2) { in eg_surface_best()
1013 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1018 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1019 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1020 surf->mtilea = 1 << (log2_int(h_over_w) >> 1); in eg_surface_best()
1287 struct radeon_surface *surf, in si_surface_sanity() argument
1293 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { in si_surface_sanity()
1298 if (surf->last_level > 15) { in si_surface_sanity()
1304 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1305 if (surf->nsamples > 1) { in si_surface_sanity()
1310 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_sanity()
1311 surf->flags |= RADEON_SURF_SET(mode, MODE); in si_surface_sanity()
1314 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) { in si_surface_sanity()
1318 if (!surf->tile_split) { in si_surface_sanity()
1320 surf->mtilea = 1; in si_surface_sanity()
1321 surf->bankw = 1; in si_surface_sanity()
1322 surf->bankh = 1; in si_surface_sanity()
1323 surf->tile_split = 64; in si_surface_sanity()
1324 surf->stencil_tile_split = 64; in si_surface_sanity()
1329 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_sanity()
1330 switch (surf->nsamples) { in si_surface_sanity()
1348 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split); in si_surface_sanity()
1350 if (surf->flags & RADEON_SURF_ZBUFFER) { in si_surface_sanity()
1351 switch (surf->nsamples) { in si_surface_sanity()
1367 } else if (surf->flags & RADEON_SURF_SCANOUT) { in si_surface_sanity()
1368 switch (surf->bpe) { in si_surface_sanity()
1379 switch (surf->bpe) { in si_surface_sanity()
1399 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
1402 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_sanity()
1405 if (surf->flags & RADEON_SURF_ZBUFFER) { in si_surface_sanity()
1407 } else if (surf->flags & RADEON_SURF_SCANOUT) { in si_surface_sanity()
1421 static void si_surf_minify(struct radeon_surface *surf, in si_surf_minify() argument
1428 surflevel->npix_x = surf->npix_x; in si_surf_minify()
1430 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level); in si_surf_minify()
1432 surflevel->npix_y = mip_minify(surf->npix_y, level); in si_surf_minify()
1433 surflevel->npix_z = mip_minify(surf->npix_z, level); in si_surf_minify()
1435 if (level == 0 && surf->last_level > 0) { in si_surf_minify()
1436 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
1437 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
1438 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d; in si_surf_minify()
1440 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
1441 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
1442 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in si_surf_minify()
1450 if (level == 0 && surf->last_level == 0) in si_surf_minify()
1453 xalign = MAX2(xalign, slice_align / surf->bpe); in si_surf_minify()
1462 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in si_surf_minify()
1466 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in si_surf_minify()
1469 static void si_surf_minify_2d(struct radeon_surface *surf, in si_surf_minify_2d() argument
1478 surflevel->npix_x = surf->npix_x; in si_surf_minify_2d()
1480 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level); in si_surf_minify_2d()
1482 surflevel->npix_y = mip_minify(surf->npix_y, level); in si_surf_minify_2d()
1483 surflevel->npix_z = mip_minify(surf->npix_z, level); in si_surf_minify_2d()
1485 if (level == 0 && surf->last_level > 0) { in si_surf_minify_2d()
1486 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify_2d()
1487 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h; in si_surf_minify_2d()
1488 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d; in si_surf_minify_2d()
1490 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in si_surf_minify_2d()
1491 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in si_surf_minify_2d()
1492 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in si_surf_minify_2d()
1495 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D && in si_surf_minify_2d()
1496 !(surf->flags & RADEON_SURF_FMASK)) { in si_surf_minify_2d()
1511 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in si_surf_minify_2d()
1514 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in si_surf_minify_2d()
1518 struct radeon_surface *surf, in si_surface_init_linear_aligned() argument
1527 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1529 xalign = MAX2(8, 64 / surf->bpe); in si_surface_init_linear_aligned()
1532 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1535 for (i = start_level; i <= surf->last_level; i++) { in si_surface_init_linear_aligned()
1536 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in si_surface_init_linear_aligned()
1537 … si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset); in si_surface_init_linear_aligned()
1539 offset = surf->bo_size; in si_surface_init_linear_aligned()
1541 offset = ALIGN(offset, surf->bo_alignment); in si_surface_init_linear_aligned()
1543 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in si_surface_init_linear_aligned()
1544 surf->tiling_index[i] = tile_mode; in si_surface_init_linear_aligned()
1551 struct radeon_surface *surf, in si_surface_init_1d() argument
1565 if (surf->flags & RADEON_SURF_SCANOUT) { in si_surface_init_1d()
1570 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in si_surface_init_1d()
1578 for (i = start_level; i <= surf->last_level; i++) { in si_surface_init_1d()
1580 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset); in si_surface_init_1d()
1582 offset = surf->bo_size; in si_surface_init_1d()
1586 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in si_surface_init_1d()
1587 if (surf->level == level) { in si_surface_init_1d()
1588 surf->tiling_index[i] = tile_mode; in si_surface_init_1d()
1590 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_1d()
1592 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_1d()
1600 struct radeon_surface *surf, in si_surface_init_1d_miptrees() argument
1605 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0); in si_surface_init_1d_miptrees()
1610 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_init_1d_miptrees()
1611 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1612 surf->stencil_offset = surf->stencil_level[0].offset; in si_surface_init_1d_miptrees()
1618 struct radeon_surface *surf, in si_surface_init_2d() argument
1635 tileb = tilew * tileh * bpe * surf->nsamples; in si_surface_init_2d()
1644 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea; in si_surface_init_2d()
1645 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea; in si_surface_init_2d()
1652 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in si_surface_init_2d()
1660 for (i = start_level; i <= surf->last_level; i++) { in si_surface_init_2d()
1662 … si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset); in si_surface_init_2d()
1681 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in si_surface_init_2d()
1684 aligned_offset = offset = surf->bo_size; in si_surface_init_2d()
1686 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); in si_surface_init_2d()
1688 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in si_surface_init_2d()
1689 if (surf->level == level) { in si_surface_init_2d()
1690 surf->tiling_index[i] = tile_mode; in si_surface_init_2d()
1692 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_2d()
1694 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_2d()
1702 struct radeon_surface *surf, in si_surface_init_2d_miptrees() argument
1713 …r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, su… in si_surface_init_2d_miptrees()
1718 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_init_2d_miptrees()
1719 …surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, s… in si_surface_init_2d_miptrees()
1720 surf->stencil_offset = surf->stencil_level[0].offset; in si_surface_init_2d_miptrees()
1726 struct radeon_surface *surf) in si_surface_init() argument
1732 if (surf->nsamples > 1) { in si_surface_init()
1733 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_init()
1734 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in si_surface_init()
1738 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in si_surface_init()
1740 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in si_surface_init()
1748 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_init()
1749 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in si_surface_init()
1754 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_init()
1759 surf->stencil_offset = 0; in si_surface_init()
1760 surf->bo_alignment = 0; in si_surface_init()
1765 r = r6_surface_init_linear(surf_man, surf, 0, 0); in si_surface_init()
1768 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in si_surface_init()
1771 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1774 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1786 struct radeon_surface *surf) in si_surface_best() argument
1791 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in si_surface_best()
1793 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) && in si_surface_best()
1794 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) { in si_surface_best()
1796 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_best()
1797 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in si_surface_best()
1800 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_best()
2117 struct radeon_surface *surf, in cik_surface_sanity() argument
2121 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { in cik_surface_sanity()
2126 if (surf->last_level > 15) { in cik_surface_sanity()
2132 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2133 if (surf->nsamples > 1) { in cik_surface_sanity()
2138 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_sanity()
2139 surf->flags |= RADEON_SURF_SET(mode, MODE); in cik_surface_sanity()
2142 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) { in cik_surface_sanity()
2146 if (!surf->tile_split) { in cik_surface_sanity()
2148 surf->mtilea = 1; in cik_surface_sanity()
2149 surf->bankw = 1; in cik_surface_sanity()
2150 surf->bankh = 1; in cik_surface_sanity()
2151 surf->tile_split = 64; in cik_surface_sanity()
2152 surf->stencil_tile_split = 64; in cik_surface_sanity()
2157 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) { in cik_surface_sanity()
2158 switch (surf->nsamples) { in cik_surface_sanity()
2173 if (surf->flags & RADEON_SURF_SBUFFER) { in cik_surface_sanity()
2176 cik_get_2d_params(surf_man, 1, surf->nsamples, false, in cik_surface_sanity()
2178 &surf->stencil_tile_split, in cik_surface_sanity()
2181 } else if (surf->flags & RADEON_SURF_SCANOUT) { in cik_surface_sanity()
2188 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_sanity()
2189 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode, in cik_surface_sanity()
2190 NULL, &surf->tile_split, NULL, &surf->mtilea, in cik_surface_sanity()
2191 &surf->bankw, &surf->bankh); in cik_surface_sanity()
2195 if (surf->flags & RADEON_SURF_SBUFFER) { in cik_surface_sanity()
2198 if (surf->flags & RADEON_SURF_ZBUFFER) { in cik_surface_sanity()
2200 } else if (surf->flags & RADEON_SURF_SCANOUT) { in cik_surface_sanity()
2215 struct radeon_surface *surf, in cik_surface_init_2d() argument
2236 tileb = surf->nsamples * tileb_1x; in cik_surface_init_2d()
2246 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea; in cik_surface_init_2d()
2247 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea; in cik_surface_init_2d()
2254 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in cik_surface_init_2d()
2262 for (i = start_level; i <= surf->last_level; i++) { in cik_surface_init_2d()
2264 … si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset); in cik_surface_init_2d()
2283 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in cik_surface_init_2d()
2286 aligned_offset = offset = surf->bo_size; in cik_surface_init_2d()
2288 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); in cik_surface_init_2d()
2290 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in cik_surface_init_2d()
2291 if (surf->level == level) { in cik_surface_init_2d()
2292 surf->tiling_index[i] = tile_mode; in cik_surface_init_2d()
2294 surf->stencil_tiling_index[i] = tile_mode; in cik_surface_init_2d()
2296 surf->stencil_tiling_index[i] = tile_mode; in cik_surface_init_2d()
2304 struct radeon_surface *surf, in cik_surface_init_2d_miptrees() argument
2310 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_init_2d_miptrees()
2311 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode, in cik_surface_init_2d_miptrees()
2314 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, in cik_surface_init_2d_miptrees()
2315 surf->tile_split, num_pipes, num_banks, 0, 0); in cik_surface_init_2d_miptrees()
2320 if (surf->flags & RADEON_SURF_SBUFFER) { in cik_surface_init_2d_miptrees()
2321 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, in cik_surface_init_2d_miptrees()
2322 surf->stencil_tile_split, num_pipes, num_banks, in cik_surface_init_2d_miptrees()
2323 surf->bo_size, 0); in cik_surface_init_2d_miptrees()
2324 surf->stencil_offset = surf->stencil_level[0].offset; in cik_surface_init_2d_miptrees()
2330 struct radeon_surface *surf) in cik_surface_init() argument
2336 if (surf->nsamples > 1) { in cik_surface_init()
2337 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_init()
2338 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in cik_surface_init()
2342 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in cik_surface_init()
2344 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in cik_surface_init()
2352 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_init()
2353 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in cik_surface_init()
2358 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_init()
2363 surf->stencil_offset = 0; in cik_surface_init()
2364 surf->bo_alignment = 0; in cik_surface_init()
2369 r = r6_surface_init_linear(surf_man, surf, 0, 0); in cik_surface_init()
2372 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in cik_surface_init()
2375 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2378 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2390 struct radeon_surface *surf) in cik_surface_best() argument
2395 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in cik_surface_best()
2397 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) && in cik_surface_best()
2398 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) { in cik_surface_best()
2400 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_best()
2401 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in cik_surface_best()
2404 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_best()
2467 struct radeon_surface *surf, in radeon_surface_sanity() argument
2471 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) { in radeon_surface_sanity()
2476 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) { in radeon_surface_sanity()
2479 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) { in radeon_surface_sanity()
2482 if (!surf->array_size) { in radeon_surface_sanity()
2486 surf->array_size = next_power_of_two(surf->array_size); in radeon_surface_sanity()
2488 switch (surf->nsamples) { in radeon_surface_sanity()
2500 if (surf->npix_y > 1) { in radeon_surface_sanity()
2505 if (surf->npix_z > 1) { in radeon_surface_sanity()
2510 if (surf->npix_z > 1) { in radeon_surface_sanity()
2515 surf->array_size = 8; in radeon_surface_sanity()
2517 surf->array_size = 6; in radeon_surface_sanity()
2523 if (surf->npix_y > 1) { in radeon_surface_sanity()
2536 struct radeon_surface *surf) in radeon_surface_init() argument
2541 type = RADEON_SURF_GET(surf->flags, TYPE); in radeon_surface_init()
2542 mode = RADEON_SURF_GET(surf->flags, MODE); in radeon_surface_init()
2544 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_init()
2548 return surf_man->surface_init(surf_man, surf); in radeon_surface_init()
2553 struct radeon_surface *surf) in radeon_surface_best() argument
2558 type = RADEON_SURF_GET(surf->flags, TYPE); in radeon_surface_best()
2559 mode = RADEON_SURF_GET(surf->flags, MODE); in radeon_surface_best()
2561 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_best()
2565 return surf_man->surface_best(surf_man, surf); in radeon_surface_best()