Lines Matching refs:R12
1023 MOV R12,#COFF_STD_2B
1024 LSL R12,#2
1026 VLD1.S32 D30[0],[R9],R12
1027 VLD1.S32 D30[1],[R9],R12
1028 VLD1.S32 D31[0],[R9],R12
1029 VLD1.S32 D31[1],[R9],R12
1055 @R12 ------
1158 MOV R12,#COFF_STD_2B @Get stride of coeffs
1165 ADD R11,R9,R12,LSL #1 @Load address of g_ai2_ihevc_trans_16[2]
1166 LSL R12,R12,#2
1168 VLD1.S16 D26,[R11],R12 @LOAD g_ai2_ihevc_trans_16[2][0-4]]
1170 VLD1.S16 D27,[R11],R12 @LOAD g_ai2_ihevc_trans_16[6][0-4]
1179 VLD1.S16 D26,[R11],R12 @LOAD g_ai2_ihevc_trans_16[10][0-4]
1185 VLD1.S16 D27,[R11],R12 @LOAD g_ai2_ihevc_trans_16[14][0-4]
1229 MOV R12,#COFF_STD_2B @Get coeffs stride
1230 LSL R12,R12,#1
1233 VLD1.S16 {d4,d5},[R11],R12 @g_ai2_ihevc_trans_16[1][0-7] -- 2 cycles
1250 VLD1.S16 {d4,d5},[R11],R12 @g_ai2_ihevc_trans_16[3][0-7]
1267 VLD1.S16 {d4,d5},[R11],R12 @g_ai2_ihevc_trans_16[5][0-7]
1269 VLD1.S16 {d6,d7},[R11],R12 @g_ai2_ihevc_trans_16[7][0-7]
1303 VLD1.S16 {d4,d5},[R11],R12 @g_ai2_ihevc_trans_16[9][0-7]
1319 VLD1.S16 {d4,d5},[R11],R12 @g_ai2_ihevc_trans_16[11][0-7]
1333 VLD1.S16 {d4,d5},[R11],R12 @g_ai2_ihevc_trans_16[13][0-7]
1335 VLD1.S16 {d2,d3},[R11],R12 @g_ai2_ihevc_trans_16[15][0-7]
1421 MOV R12,#COFF_STD_W
1422 LSL R12,R12,#2
1423 VLD1.S32 D28,[R9],R12
1424 VLD1.S32 D29,[R9],R12
1425 VLD1.S32 D30,[R9],R12
1426 VLD1.S32 D31,[R9],R12
1427 SUB R9,R9,R12,LSL #2
1510 MOV R12,#COFF_STD_W
1511 ADD R11,R9,R12,LSL #1 @Get to the 2nd row of src
1512 LSL R12,R12,#2
1514 …VLD1.S32 {D14,D15},[R11],R12 @LOAD g_ai2_ihevc_trans_16[2][0-4] -> 2G0 2G1 2G2 2G3, 2-cycle…
1524 VLD1.S32 {D16,D17},[R11],R12 @LOAD g_ai2_ihevc_trans_16[6][0-4]
1550 VLD1.S32 {D14,D15},[R11],R12 @LOAD g_ai2_ihevc_trans_16[10][0-4]
1556 VLD1.S32 {D16,D17},[R11],R12 @LOAD g_ai2_ihevc_trans_16[14][0-4]
1567 MOV R12,#COFF_STD_W
1568 ADD R11,R9,R12 @Get 1ST row
1569 LSL R12,R12,#1
1579 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[1][0-7]
1596 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[3][0-7]
1603 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[5][0-7]
1610 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[7][0-7]
1624 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[0][0-7]
1641 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[1][0-7]
1654 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[2][0-7]
1662 VLD1.S32 {Q2,Q3},[R11],R12 @g_ai2_ihevc_trans_16[3][0-7]