Lines Matching refs:VREV64
1105 VREV64.S16 Q5,Q5 @Rev row 1
1106 VREV64.S16 Q7,Q7 @Rev row 2
1115 VREV64.S16 D24,D17 @rev e[k] k-> 4-7 row 1
1116 VREV64.S16 D25,D21 @rev e[k] k-> 4-7 row 2
1429 VREV64.32 Q15,Q15
1450 VREV64.S32 Q2,Q2 @Rev 9-12 R1
1451 VREV64.S32 Q3,Q3 @Rev 12-16 R1
1452 VREV64.S32 Q6,Q6 @Rev 9-12 R2
1453 VREV64.S32 Q7,Q7 @Rev 12-16 R2
1465 VREV64.S32 Q9 ,Q9 @rev e[k] k-> 4-7 R1, dual issued with prev. instruction
1470 VREV64.S32 Q13,Q13 @rev e[k] k-> 4-7 R2, dual issued with prev. instruction
1479 VREV64.S32 D5,D5 @rev ee[k] 4-7 R1, dual issued with prev. instruction
1483 VREV64.S32 D9,D9 @rev ee[k] 4-7 R2, dual issued with prev. instruction
1490 …VREV64.S32 Q8,Q6 @Q6 : eee[0] eee[1] eeo[0] eeo[1] R1 -> ;Q8 : eee[1] eee…
1492 …VREV64.S32 Q9,Q7 @Q7 : eee[0] eee[1] eeo[0] eeo[1] R2 -> ;Q9 : eee[1] ee…