Lines Matching refs:lanes

117                                                             all lanes in its group.
129                                                             1, 2, 4, 8 or 16 lanes.
132 …                                          Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.
988 Selects which lanes to pull data from, within a group of 8 lanes. This is a mandatory modifier.
1004     dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}]  Select lanes to read from.
1019 Controls interaction with inactive lanes for *dpp8* instructions. The default value is zero.
1021 Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.
1028     fi:0                                 Fetch zero when accessing data from inactive lanes.
1029     fi:1                                 Fetch pre-exist values from inactive lanes.
1050 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1090 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1100                                              lanes in the row.
1125 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1156 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1184 invalid lanes is disabled.
1189     bound_ctrl:0                             Enables data sharing with invalid lanes.
1200 Controls interaction with *inactive* lanes for *dpp16* instructions. The default value is zero.
1202 Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.
1209     fi:0                                     Interaction with inactive lanes is controlled by
1212     fi:1                                     Fetch pre-exist values from inactive lanes.