Lines Matching refs:RegIdx
109 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
110 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
112 WorklistMembers.set(RegIdx); in PutInWorklist()
113 Worklist.push_back(RegIdx); in PutInWorklist()
360 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
361 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
362 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
493 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
494 unsigned Reg = Register::index2VirtReg(RegIdx); in runOnce()
497 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
504 unsigned RegIdx = Worklist.front(); in runOnce() local
506 WorklistMembers.reset(RegIdx); in runOnce()
507 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
508 unsigned Reg = Register::index2VirtReg(RegIdx); in runOnce()
519 LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0; in runOnce()
520 RegIdx < NumVirtRegs; in runOnce()
521 ++RegIdx) { in runOnce()
522 unsigned Reg = Register::index2VirtReg(RegIdx); in runOnce()
523 const VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
539 unsigned RegIdx = Register::virtReg2Index(Reg); in runOnce() local
540 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce()