Lines Matching refs:Reg
96 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument
97 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
114 static Register performCopyPropagation(Register Reg, in performCopyPropagation() argument
119 int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI); in performCopyPropagation()
122 return Reg; in performCopyPropagation()
126 return Reg; in performCopyPropagation()
132 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation()
134 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation()
141 return Reg; in performCopyPropagation()
144 if (!DestSrc || DestSrc->Destination->getReg() != Reg) in performCopyPropagation()
145 return Reg; in performCopyPropagation()
149 if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg)) in performCopyPropagation()
150 return Reg; in performCopyPropagation()
153 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI) in performCopyPropagation()
182 void recordReload(Register Reg, int FI, const MachineBasicBlock *MBB) { in recordReload() argument
183 RegSlotPair RSP(Reg, FI); in recordReload()
190 bool hasReload(Register Reg, int FI, const MachineBasicBlock *MBB) { in hasReload() argument
191 RegSlotPair RSP(Reg, FI); in hasReload()
250 int getFrameIndex(Register Reg, MachineBasicBlock *EHPad) { in getFrameIndex() argument
256 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex()
260 << printReg(Reg, &TRI) << " at " in getFrameIndex()
267 unsigned Size = getRegisterSize(TRI, Reg); in getFrameIndex()
289 GlobalIndices[EHPad].push_back(std::make_pair(Reg, FI)); in getFrameIndex()
291 << printReg(Reg, &TRI) << " at landing pad " in getFrameIndex()
366 bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; } in isCalleeSaved() argument
385 Register Reg = MO.getReg(); in findRegistersToSpill() local
386 assert(Reg.isPhysical() && "Only physical regs are expected"); in findRegistersToSpill()
388 if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !is_contained(GCRegs, Reg))) in findRegistersToSpill()
391 LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index " in findRegistersToSpill()
394 if (VisitedRegs.insert(Reg).second) in findRegistersToSpill()
395 RegsToSpill.push_back(Reg); in findRegistersToSpill()
405 for (Register Reg : RegsToSpill) { in spillRegisters() local
406 int FI = CacheFI.getFrameIndex(Reg, EHPad); in spillRegisters()
407 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in spillRegisters()
410 RegToSlotIdx[Reg] = FI; in spillRegisters()
412 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI in spillRegisters()
418 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
421 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, in spillRegisters()
426 void insertReloadBefore(unsigned Reg, MachineBasicBlock::iterator It, in insertReloadBefore() argument
428 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in insertReloadBefore()
429 int FI = RegToSlotIdx[Reg]; in insertReloadBefore()
431 TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI); in insertReloadBefore()
439 TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI); in insertReloadBefore()
443 assert(TII.isLoadFromStackSlot(*Reload, Dummy) == Reg); in insertReloadBefore()
454 for (auto Reg : RegsToReload) { in insertReloads() local
455 insertReloadBefore(Reg, InsertPoint, MBB); in insertReloads()
456 LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI " in insertReloads()
457 << RegToSlotIdx[Reg] << " after statepoint\n"); in insertReloads()
459 if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) { in insertReloads()
460 RC.recordReload(Reg, RegToSlotIdx[Reg], EHPad); in insertReloads()
462 insertReloadBefore(Reg, EHPadInsertPoint, EHPad); in insertReloads()
484 Register Reg = DefMO.getReg(); in rewriteStatepoint() local
486 assert(is_contained(RegsToSpill, Reg)); in rewriteStatepoint()
487 RegsToReload.push_back(Reg); in rewriteStatepoint()
489 if (isCalleeSaved(Reg)) { in rewriteStatepoint()
491 MIB.addReg(Reg, RegState::Define); in rewriteStatepoint()
494 RegsToReload.push_back(Reg); in rewriteStatepoint()