Lines Matching refs:MIRBuilder
289 MachineIRBuilder &MIRBuilder) { in translateBinaryOp() argument
303 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
308 MachineIRBuilder &MIRBuilder) { in translateUnaryOp() argument
316 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
320 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) { in translateFNeg() argument
321 return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder); in translateFNeg()
325 MachineIRBuilder &MIRBuilder) { in translateCompare() argument
334 MIRBuilder.buildICmp(Pred, Res, Op0, Op1); in translateCompare()
336 MIRBuilder.buildCopy( in translateCompare()
339 MIRBuilder.buildCopy( in translateCompare()
343 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, in translateCompare()
350 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) { in translateRet() argument
363 &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg()); in translateRet()
369 return CLI->lowerReturn(MIRBuilder, Ret, VRegs, SwiftErrorVReg); in translateRet()
561 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) { in translateBr() argument
563 auto &CurMBB = MIRBuilder.getMBB(); in translateBr()
569 MIRBuilder.buildBr(*Succ0MBB); in translateBr()
1235 MachineIRBuilder &MIRBuilder) { in translateIndirectBr() argument
1239 MIRBuilder.buildBrIndirect(Tgt); in translateIndirectBr()
1243 MachineBasicBlock &CurBB = MIRBuilder.getMBB(); in translateIndirectBr()
1264 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) { in translateLoad() argument
1278 Register VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(), in translateLoad()
1280 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1291 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8); in translateLoad()
1301 MIRBuilder.buildLoad(Regs[i], Addr, *MMO); in translateLoad()
1307 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) { in translateStore() argument
1322 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(), in translateStore()
1324 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1333 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8); in translateStore()
1343 MIRBuilder.buildStore(Vals[i], Addr, *MMO); in translateStore()
1373 MachineIRBuilder &MIRBuilder) { in translateExtractValue() argument
1388 MachineIRBuilder &MIRBuilder) { in translateInsertValue() argument
1408 MachineIRBuilder &MIRBuilder) { in translateSelect() argument
1419 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
1426 MachineIRBuilder &MIRBuilder) { in translateCopy() argument
1435 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1441 MachineIRBuilder &MIRBuilder) { in translateBitCast() argument
1445 return translateCopy(U, *U.getOperand(0), MIRBuilder); in translateBitCast()
1447 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder); in translateBitCast()
1451 MachineIRBuilder &MIRBuilder) { in translateCast() argument
1454 MIRBuilder.buildInstr(Opcode, {Res}, {Op}); in translateCast()
1459 MachineIRBuilder &MIRBuilder) { in translateGetElementPtr() argument
1477 MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg) in translateGetElementPtr()
1504 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset); in translateGetElementPtr()
1505 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0)) in translateGetElementPtr()
1514 IdxReg = MIRBuilder.buildSplatVector( in translateGetElementPtr()
1518 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0); in translateGetElementPtr()
1525 auto ElementSizeMIB = MIRBuilder.buildConstant( in translateGetElementPtr()
1528 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0); in translateGetElementPtr()
1532 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0); in translateGetElementPtr()
1538 MIRBuilder.buildConstant(OffsetTy, Offset); in translateGetElementPtr()
1539 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0)); in translateGetElementPtr()
1543 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1548 MachineIRBuilder &MIRBuilder, in translateMemFunc() argument
1571 SizeOpReg = MIRBuilder.buildZExtOrTrunc(SizeTy, SizeOpReg).getReg(0); in translateMemFunc()
1573 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1613 MachineIRBuilder &MIRBuilder) { in getStackGuard() argument
1617 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); in getStackGuard()
1634 MachineIRBuilder &MIRBuilder) { in translateOverflowIntrinsic() argument
1636 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1644 MachineIRBuilder &MIRBuilder) { in translateFixedPointIntrinsic() argument
1649 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
1752 MachineIRBuilder &MIRBuilder) { in translateSimpleIntrinsic() argument
1765 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
1793 const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) { in translateConstrainedFPIntrinsic() argument
1811 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags); in translateConstrainedFPIntrinsic()
1816 MachineIRBuilder &MIRBuilder) { in translateKnownIntrinsic() argument
1820 if (translateSimpleIntrinsic(CI, ID, MIRBuilder)) in translateKnownIntrinsic()
1850 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI)); in translateKnownIntrinsic()
1865 MIRBuilder.getDebugLoc()) && in translateKnownIntrinsic()
1876 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), in translateKnownIntrinsic()
1886 MIRBuilder.getDebugLoc()) && in translateKnownIntrinsic()
1889 MIRBuilder.buildDbgLabel(DI.getLabel()); in translateKnownIntrinsic()
1902 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) in translateKnownIntrinsic()
1913 MIRBuilder.getDebugLoc()) && in translateKnownIntrinsic()
1918 MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression()); in translateKnownIntrinsic()
1920 MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression()); in translateKnownIntrinsic()
1927 MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression()); in translateKnownIntrinsic()
1933 return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder); in translateKnownIntrinsic()
1935 return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder); in translateKnownIntrinsic()
1937 return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder); in translateKnownIntrinsic()
1939 return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder); in translateKnownIntrinsic()
1941 return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder); in translateKnownIntrinsic()
1943 return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder); in translateKnownIntrinsic()
1945 return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1947 return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1949 return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1951 return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1953 return translateBinaryOp(TargetOpcode::G_USHLSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1955 return translateBinaryOp(TargetOpcode::G_SSHLSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1957 return translateBinaryOp(TargetOpcode::G_UMIN, CI, MIRBuilder); in translateKnownIntrinsic()
1959 return translateBinaryOp(TargetOpcode::G_UMAX, CI, MIRBuilder); in translateKnownIntrinsic()
1961 return translateBinaryOp(TargetOpcode::G_SMIN, CI, MIRBuilder); in translateKnownIntrinsic()
1963 return translateBinaryOp(TargetOpcode::G_SMAX, CI, MIRBuilder); in translateKnownIntrinsic()
1966 return translateUnaryOp(TargetOpcode::G_ABS, CI, MIRBuilder); in translateKnownIntrinsic()
1968 return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIX, CI, MIRBuilder); in translateKnownIntrinsic()
1970 return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIX, CI, MIRBuilder); in translateKnownIntrinsic()
1972 return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIXSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1974 return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIXSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1976 return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIX, CI, MIRBuilder); in translateKnownIntrinsic()
1978 return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIX, CI, MIRBuilder); in translateKnownIntrinsic()
1980 return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIXSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1982 return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder); in translateKnownIntrinsic()
1995 MIRBuilder.buildFMA(Dst, Op0, Op1, Op2, in translateKnownIntrinsic()
1999 auto FMul = MIRBuilder.buildFMul( in translateKnownIntrinsic()
2001 MIRBuilder.buildFAdd(Dst, FMul, Op2, in translateKnownIntrinsic()
2008 MIRBuilder.buildFPExt(getOrCreateVReg(CI), in translateKnownIntrinsic()
2014 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI), in translateKnownIntrinsic()
2019 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY); in translateKnownIntrinsic()
2021 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMMOVE); in translateKnownIntrinsic()
2023 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMSET); in translateKnownIntrinsic()
2028 MIRBuilder.buildConstant(Reg, TypeID); in translateKnownIntrinsic()
2038 getStackGuard(getOrCreateVReg(CI), MIRBuilder); in translateKnownIntrinsic()
2043 getStackGuard(GuardVal, MIRBuilder); in translateKnownIntrinsic()
2049 MIRBuilder.buildStore( in translateKnownIntrinsic()
2068 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
2082 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
2094 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2101 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()
2112 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2124 MIRBuilder in translateKnownIntrinsic()
2131 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER) in translateKnownIntrinsic()
2154 MIRBuilder.buildInstrNoInsert(TargetOpcode::LOCAL_ESCAPE) in translateKnownIntrinsic()
2176 MIRBuilder.buildInstr(Opc, {Dst}, {ScalarSrc, VecSrc}, in translateKnownIntrinsic()
2191 auto Rdx = MIRBuilder.buildInstr( in translateKnownIntrinsic()
2193 MIRBuilder.buildInstr(ScalarOpc, {Dst}, {ScalarSrc, Rdx}, in translateKnownIntrinsic()
2202 MIRBuilder); in translateKnownIntrinsic()
2209 MachineIRBuilder &MIRBuilder) { in translateInlineAsm() argument
2220 MIRBuilder, CB, [&](const Value &Val) { return getOrCreateVRegs(Val); }); in translateInlineAsm()
2224 MachineIRBuilder &MIRBuilder) { in translateCallBase() argument
2235 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallBase()
2236 &CB, &MIRBuilder.getMBB(), Arg)); in translateCallBase()
2239 SwiftError.getOrCreateVRegDefAt(&CB, &MIRBuilder.getMBB(), Arg); in translateCallBase()
2249 CLI->lowerCall(MIRBuilder, CB, Res, Args, SwiftErrorVReg, in translateCallBase()
2256 HasTailCall = TII->isTailCall(*std::prev(MIRBuilder.getInsertPt())); in translateCallBase()
2262 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { in translateCall() argument
2278 return translateInlineAsm(CI, MIRBuilder); in translateCall()
2288 return translateCallBase(CI, MIRBuilder); in translateCall()
2292 if (translateKnownIntrinsic(CI, ID, MIRBuilder)) in translateCall()
2302 MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory()); in translateCall()
2349 MachineIRBuilder &MIRBuilder) { in translateInvoke() argument
2379 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol); in translateInvoke()
2381 if (!translateCallBase(I, MIRBuilder)) in translateInvoke()
2385 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol); in translateInvoke()
2391 MIRBuilder.getMBB().addSuccessor(&ReturnMBB); in translateInvoke()
2392 MIRBuilder.getMBB().addSuccessor(&EHPadMBB); in translateInvoke()
2393 MIRBuilder.buildBr(ReturnMBB); in translateInvoke()
2399 MachineIRBuilder &MIRBuilder) { in translateCallBr() argument
2405 MachineIRBuilder &MIRBuilder) { in translateLandingPad() argument
2408 MachineBasicBlock &MBB = MIRBuilder.getMBB(); in translateLandingPad()
2429 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL) in translateLandingPad()
2440 MIRBuilder.buildUndef(Undef); in translateLandingPad()
2454 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
2462 MIRBuilder.buildCopy(PtrVReg, SelectorReg); in translateLandingPad()
2463 MIRBuilder.buildCast(ResRegs[1], PtrVReg); in translateLandingPad()
2469 MachineIRBuilder &MIRBuilder) { in translateAlloca() argument
2478 MIRBuilder.buildFrameIndex(Res, FI); in translateAlloca()
2492 MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts); in translateAlloca()
2501 MIRBuilder.buildMul(AllocSize, NumElts, TySize); in translateAlloca()
2507 auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign.value() - 1); in translateAlloca()
2508 auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne, in translateAlloca()
2511 MIRBuilder.buildConstant(IntPtrTy, ~(uint64_t)(StackAlign.value() - 1)); in translateAlloca()
2512 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst); in translateAlloca()
2517 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment); in translateAlloca()
2524 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) { in translateVAArg() argument
2529 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)}, in translateVAArg()
2536 MachineIRBuilder &MIRBuilder) { in translateInsertElement() argument
2540 return translateCopy(U, *U.getOperand(1), MIRBuilder); in translateInsertElement()
2546 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx); in translateInsertElement()
2551 MachineIRBuilder &MIRBuilder) { in translateExtractElement() argument
2555 return translateCopy(U, *U.getOperand(0), MIRBuilder); in translateExtractElement()
2573 Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0); in translateExtractElement()
2575 MIRBuilder.buildExtractVectorElement(Res, Val, Idx); in translateExtractElement()
2580 MachineIRBuilder &MIRBuilder) { in translateShuffleVector() argument
2587 MIRBuilder in translateShuffleVector()
2595 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) { in translatePHI() argument
2600 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {}); in translatePHI()
2609 MachineIRBuilder &MIRBuilder) { in translateAtomicCmpXchg() argument
2628 MIRBuilder.buildAtomicCmpXchgWithSuccess( in translateAtomicCmpXchg()
2638 MachineIRBuilder &MIRBuilder) { in translateAtomicRMW() argument
2697 MIRBuilder.buildAtomicRMW( in translateAtomicRMW()
2707 MachineIRBuilder &MIRBuilder) { in translateFence() argument
2709 MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()), in translateFence()
2715 MachineIRBuilder &MIRBuilder) { in translateFreeze() argument
2723 MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]); in translateFreeze()