1376   ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);  in translateExtractValue()  local
1382     DstRegs[i] = SrcRegs[Idx++];  in translateExtractValue()
1393   ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);  in translateInsertValue()  local
1401       DstRegs[i] = SrcRegs[i];  in translateInsertValue()
1555   SmallVector<Register, 3> SrcRegs;  in translateMemFunc()  local
1563     SrcRegs.push_back(SrcReg);  in translateMemFunc()
1569   Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1];  in translateMemFunc()
1574   for (Register SrcReg : SrcRegs)  in translateMemFunc()
2717   const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0));  in translateFreeze()  local
2719   assert(DstRegs.size() == SrcRegs.size() &&  in translateFreeze()
2723     MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]);  in translateFreeze()