812 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,  in findInlineAsmFlagIdx()  argument
815   assert(OpIdx < getNumOperands() && "OpIdx out of range");  in findInlineAsmFlagIdx()
818   if (OpIdx < InlineAsm::MIOp_FirstOperand)  in findInlineAsmFlagIdx()
830     if (i + NumOps > OpIdx) {  in findInlineAsmFlagIdx()
875 MachineInstr::getRegClassConstraint(unsigned OpIdx,  in getRegClassConstraint()  argument
884     return TII->getRegClass(getDesc(), OpIdx, TRI, MF);  in getRegClassConstraint()
886   if (!getOperand(OpIdx).isReg())  in getRegClassConstraint()
891   if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))  in getRegClassConstraint()
892     OpIdx = DefIdx;  in getRegClassConstraint()
895   int FlagIdx = findInlineAsmFlagIdx(OpIdx);  in getRegClassConstraint()
932     unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,  in getRegClassConstraintEffectForVRegImpl()  argument
936   const MachineOperand &MO = getOperand(OpIdx);  in getRegClassConstraintEffectForVRegImpl()
940   return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);  in getRegClassConstraintEffectForVRegImpl()
944     unsigned OpIdx, const TargetRegisterClass *CurRC,  in getRegClassConstraintEffect()  argument
946   const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);  in getRegClassConstraintEffect()
947   const MachineOperand &MO = getOperand(OpIdx);  in getRegClassConstraintEffect()
1121 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {  in findTiedOperandIdx()
1122   const MachineOperand &MO = getOperand(OpIdx);  in findTiedOperandIdx()
1137       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)  in findTiedOperandIdx()
1153       if (OpIdx == CurDefIdx)  in findTiedOperandIdx()
1155       if (OpIdx == CurUseIdx)  in findTiedOperandIdx()
1175     if (OpIdx > i && OpIdx < i + NumOps)  in findTiedOperandIdx()
1186       return OpIdx - Delta;  in findTiedOperandIdx()
1190       return OpIdx + Delta;  in findTiedOperandIdx()
1514 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,  in getTypeToPrint()  argument
1516   const MachineOperand &Op = getOperand(OpIdx);  in getTypeToPrint()
1520   if (isVariadic() || OpIdx >= getNumExplicitOperands())  in getTypeToPrint()
1523   auto &OpInfo = getDesc().OpInfo[OpIdx];  in getTypeToPrint()
1608   auto getTiedOperandIdx = [&](unsigned OpIdx) {  in print()  argument
1611     const MachineOperand &MO = getOperand(OpIdx);  in print()
1613       return findTiedOperandIdx(OpIdx);  in print()
1684     const unsigned OpIdx = InlineAsm::MIOp_AsmString;  in print()  local
1685     LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};  in print()
1686     unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);  in print()
1687     getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,  in print()
1922     unsigned OpIdx = DeadOps.back();  in addRegisterKilled()  local
1923     if (getOperand(OpIdx).isImplicit() &&  in addRegisterKilled()
1924         (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))  in addRegisterKilled()
1925       RemoveOperand(OpIdx);  in addRegisterKilled()
1927       getOperand(OpIdx).setIsKill(false);  in addRegisterKilled()
1987     unsigned OpIdx = DeadOps.back();  in addRegisterDead()  local
1988     if (getOperand(OpIdx).isImplicit() &&  in addRegisterDead()
1989         (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))  in addRegisterDead()
1990       RemoveOperand(OpIdx);  in addRegisterDead()
1992       getOperand(OpIdx).setIsDead(false);  in addRegisterDead()