171     if (MO.isReg())  in RemoveRegOperandsFromUseLists()
180     if (MO.isReg())  in AddRegOperandsToUseLists()
227   bool isImpReg = Op.isReg() && Op.isImplicit();  in addOperand()
229     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {  in addOperand()
275   if (NewMO->isReg()) {  in addOperand()
310     if (Operands[i].isReg())  in RemoveOperand()
315   if (MRI && Operands[OpNo].isReg())  in RemoveOperand()
625     if (!MO.isReg()) {  in isIdenticalTo()
692     if (!MO.isReg() || !MO.isDef())  in eraseFromParentAndMarkDBGValuesForRemoval()
740     if (MO.isReg() && MO.isImplicit())  in getNumExplicitOperands()
754     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())  in getNumExplicitDefs()
886   if (!getOperand(OpIdx).isReg())  in getRegClassConstraint()
937   if (!MO.isReg() || MO.getReg() != Reg)  in getRegClassConstraintEffectForVRegImpl()
948   assert(MO.isReg() &&  in getRegClassConstraintEffect()
978     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)  in hasRegisterImplicitUseOperand()
991     if (!MO.isReg() || !MO.isUse())  in findRegisterUseOperandIdx()
1015     if (!MO.isReg() || MO.getReg() != Reg)  in readsWritesVirtualRegister()
1045     if (!MO.isReg() || !MO.isDef())  in findRegisterDefOperandIdx()
1137       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)  in findTiedOperandIdx()
1151       while (!getOperand(CurUseIdx).isReg())  in findTiedOperandIdx()
1199     if (MO.isReg() && MO.isUse())  in clearKillInfo()
1211       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1217       if (!MO.isReg() || MO.getReg() != FromReg)  in substituteRegister()
1477     if (!MO.isReg() || MO.isUse())  in allDefsAreDead()
1492     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())  in copyImplicitOps()
1503     if (!Operand.isReg() || Operand.isDef())  in hasComplexRegisterTies()
1517   if (!Op.isReg())  in getTypeToPrint()
1557     if (!MO.isReg() || MO.isDef())  in dumprImpl()
1612     if (MO.isReg() && MO.isTied() && !MO.isDef())  in print()
1622     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())  in print()
1887     if (!MO.isReg() || !MO.isUse() || MO.isUndef())  in addRegisterKilled()
1948     if (!MO.isReg() || !MO.isUse() || !MO.isKill())  in clearRegisterKills()
1966     if (!MO.isReg() || !MO.isDef())  in addRegisterDead()
2011     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)  in clearRegisterDeads()
2019     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)  in setRegisterDefReadUndef()
2033       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&  in addRegisterDefined()
2051     if (!MO.isReg() || !MO.isDef()) continue;  in setPhysRegsDeadExcept()
2076     if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))  in getHashValue()
2130   if (MO.isReg())  in BuildMI()
2166   assert(MI.getOperand(0).isReg() && "can't spill non-register");  in computeExprForSpill()
2201   if (!MI.getOperand(0).isReg())  in collectDebugValues()
2218   if (!getOperand(0).isReg())  in changeDebugValuesDefReg()