616       OrderedInsts.push_back(SU->getInstr());  in schedule()
617       Cycles[SU->getInstr()] = Cycle;  in schedule()
618       Stages[SU->getInstr()] = Schedule.stageScheduled(SU);  in schedule()
744     MachineInstr &MI = *SU.getInstr();  in addLoopCarriedDependences()
769           MachineInstr &LdMI = *Load->getInstr();  in addLoopCarriedDependences()
846     MachineInstr *MI = I.getInstr();  in updatePhiDependences()
902       MachineInstr *PMI = PI.getSUnit()->getInstr();  in updatePhiDependences()
904         if (I.getInstr()->isPHI()) {  in updatePhiDependences()
927     if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase,  in changeDependences()
932     Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();  in changeDependences()
1246           (SI.getKind() == SDep::Anti && !SI.getSUnit()->getInstr()->isPHI()))  in createAdjacencyStructure()
1257       if (!SUnits[i].getInstr()->mayStore() ||  in createAdjacencyStructure()
1260       if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) {  in createAdjacencyStructure()
1372     if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence())  in apply()
1382       MachineInstr *TmpMI = TmpSU->getInstr();  in apply()
1406         MachineInstr *TmpMI = TmpSU->getInstr();  in apply()
1634     const MachineInstr *MI = SU->getInstr();  in computeLiveOuts()
1649     for (const MachineOperand &MO : SU->getInstr()->operands())  in computeLiveOuts()
1690       MachineBasicBlock::const_iterator CurInstI = SU->getInstr();  in registerPressureFilter()
1695       RecRPTracker.getMaxUpwardPressureDelta(SU->getInstr(), nullptr, RPDelta,  in registerPressureFilter()
2078         SU->getInstr()->dump();  in schedulePipeline()
2101         if (SU->getInstr()->isPHI())  in schedulePipeline()
2313   MachineInstr *SI = Source->getInstr();  in isLoopCarriedDep()
2314   MachineInstr *DI = Dep.getSUnit()->getInstr();  in isLoopCarriedDep()
2411         if (ST.getInstrInfo()->isZeroCost((*I)->getInstr()->getOpcode()))  in insert()
2413         assert(ProcItinResources.canReserveResources(*(*I)->getInstr()) &&  in insert()
2415         ProcItinResources.reserveResources(*(*I)->getInstr());  in insert()
2418     if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()) ||  in insert()
2419         ProcItinResources.canReserveResources(*SU->getInstr())) {  in insert()
2422         SU->getInstr()->dump();  in insert()
2435       SU->getInstr()->dump();  in insert()
2492     if (DAG->isBackedge(SU, P) && P.getSUnit()->getInstr()->isPHI())  in multipleIterations()
2494         if (S.getKind() == SDep::Data && S.getSUnit()->getInstr()->isPHI())  in multipleIterations()
2533         if (BE && Dep.getSUnit() == BE && !SU->getInstr()->isPHI() &&  in computeStart()
2564   MachineInstr *MI = SU->getInstr();  in orderDependence()
2588           (*I)->getInstr()->readsWritesVirtualRegister(Reg);  in orderDependence()
2620                  isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {  in orderDependence()
2705   if (UseSU->getInstr()->isPHI())  in isLoopCarried()
2810       if (!PredSU->getInstr()->isPHI() && PredIndex < Index) {  in checkValidNodeOrder()
2826       if (!SuccSU->getInstr()->isPHI() && SuccIndex < Index) {  in checkValidNodeOrder()
2833     if (PredBefore && SuccBefore && !SU->getInstr()->isPHI()) {  in checkValidNodeOrder()
2867     MachineInstr *MI = SU->getInstr();  in fixupRegisterOverlaps()
2935     SSD->applyInstrChange(SU->getInstr(), *this);  in finalizeSchedule()
2945       if (SU->getInstr()->isPHI())  in finalizeSchedule()
2951       if (!SU->getInstr()->isPHI())  in finalizeSchedule()
2967     os << "   SU(" << I->NodeNum << ") " << *(I->getInstr());  in print()
2981       CI->getInstr()->print(os);  in print()