Lines Matching refs:Reg
58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
60 VRegInfo[Reg].first = RC; in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
85 MachineRegisterInfo::constrainRegClass(Register Reg, in constrainRegClass() argument
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
95 const LLT RegTy = getType(Reg); in constrainRegAttrs()
102 const auto RegCB = getRegClassOrRegBank(Reg); in constrainRegAttrs()
104 setRegClassOrRegBank(Reg, ConstrainingRegCB); in constrainRegAttrs()
110 *this, Reg, RegCB.get<const TargetRegisterClass *>(), in constrainRegAttrs()
117 setType(Reg, ConstrainingRegTy); in constrainRegAttrs()
122 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass() argument
124 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
133 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
142 setRegClass(Reg, NewRC); in recomputeRegClass()
147 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister() local
148 VRegInfo.grow(Reg); in createIncompleteVirtualRegister()
149 RegAllocHints.grow(Reg); in createIncompleteVirtualRegister()
150 insertVRegByName(Name, Reg); in createIncompleteVirtualRegister()
151 return Reg; in createIncompleteVirtualRegister()
165 Register Reg = createIncompleteVirtualRegister(Name); in createVirtualRegister() local
166 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
168 TheDelegate->MRI_NoteNewVirtualRegister(Reg); in createVirtualRegister()
169 return Reg; in createVirtualRegister()
174 Register Reg = createIncompleteVirtualRegister(Name); in cloneVirtualRegister() local
175 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
176 setType(Reg, getType(VReg)); in cloneVirtualRegister()
178 TheDelegate->MRI_NoteNewVirtualRegister(Reg); in cloneVirtualRegister()
179 return Reg; in cloneVirtualRegister()
190 Register Reg = createIncompleteVirtualRegister(Name); in createGenericVirtualRegister() local
192 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); in createGenericVirtualRegister()
193 setType(Reg, Ty); in createGenericVirtualRegister()
195 TheDelegate->MRI_NoteNewVirtualRegister(Reg); in createGenericVirtualRegister()
196 return Reg; in createGenericVirtualRegister()
205 Register Reg = Register::index2VirtReg(i); in clearVirtRegs() local
206 if (!VRegInfo[Reg].second) in clearVirtRegs()
208 verifyUseList(Reg); in clearVirtRegs()
217 void MachineRegisterInfo::verifyUseList(Register Reg) const { in verifyUseList()
220 for (MachineOperand &M : reg_operands(Reg)) { in verifyUseList()
224 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
233 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
239 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
244 if (MO->getReg() != Reg) { in verifyUseList()
245 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
276 MO->Contents.Reg.Prev = MO; in addRegOperandToUseList()
277 MO->Contents.Reg.Next = nullptr; in addRegOperandToUseList()
284 MachineOperand *Last = Head->Contents.Reg.Prev; in addRegOperandToUseList()
287 Head->Contents.Reg.Prev = MO; in addRegOperandToUseList()
288 MO->Contents.Reg.Prev = Last; in addRegOperandToUseList()
294 MO->Contents.Reg.Next = Head; in addRegOperandToUseList()
298 MO->Contents.Reg.Next = nullptr; in addRegOperandToUseList()
299 Last->Contents.Reg.Next = MO; in addRegOperandToUseList()
311 MachineOperand *Next = MO->Contents.Reg.Next; in removeRegOperandFromUseList()
312 MachineOperand *Prev = MO->Contents.Reg.Prev; in removeRegOperandFromUseList()
318 Prev->Contents.Reg.Next = Next; in removeRegOperandFromUseList()
320 (Next ? Next : Head)->Contents.Reg.Prev = Prev; in removeRegOperandFromUseList()
322 MO->Contents.Reg.Prev = nullptr; in removeRegOperandFromUseList()
323 MO->Contents.Reg.Next = nullptr; in removeRegOperandFromUseList()
353 MachineOperand *Prev = Src->Contents.Reg.Prev; in moveOperands()
354 MachineOperand *Next = Src->Contents.Reg.Next; in moveOperands()
363 Prev->Contents.Reg.Next = Dst; in moveOperands()
367 (Next ? Next : Head)->Contents.Reg.Prev = Dst; in moveOperands()
400 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const { in getVRegDef()
402 def_instr_iterator I = def_instr_begin(Reg); in getVRegDef()
411 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { in getUniqueVRegDef()
412 if (def_empty(Reg)) return nullptr; in getUniqueVRegDef()
413 def_instr_iterator I = def_instr_begin(Reg); in getUniqueVRegDef()
437 void MachineRegisterInfo::clearKillFlags(Register Reg) const { in clearKillFlags()
438 for (MachineOperand &MO : use_operands(Reg)) in clearKillFlags()
442 bool MachineRegisterInfo::isLiveIn(Register Reg) const { in isLiveIn()
444 if ((Register)I->first == Reg || I->second == Reg) in isLiveIn()
499 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const { in getMaxLaneMaskForVReg()
501 assert(Register::isVirtualRegister(Reg)); in getMaxLaneMaskForVReg()
502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg()
507 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { in dumpUses()
508 for (MachineInstr &I : use_instructions(Reg)) in dumpUses()
545 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const { in markUsesInDebugValueAsUndef()
548 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); in markUsesInDebugValueAsUndef()
553 UseMI->getDebugOperandForReg(Reg)->setReg(0U); in markUsesInDebugValueAsUndef()
613 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { in disableCalleeSavedRegister() argument
616 assert(Reg && (Reg < TRI->getNumRegs()) && in disableCalleeSavedRegister()
632 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in disableCalleeSavedRegister()
648 for (MCPhysReg Reg : CSRs) in setCalleeSavedRegs() local
649 UpdatedCSRs.push_back(Reg); in setCalleeSavedRegs()
663 MCRegister Reg = *Super; in isReservedRegUnit() local
664 if (!isReserved(Reg)) { in isReservedRegUnit()