Lines Matching refs:Def
258 RegSubRegPair Def, RewriteMapTy &RewriteMap);
370 const MachineInstr *Def = nullptr; member in __anond9421e600111::ValueTracker
426 Def = MRI.getVRegDef(Reg); in ValueTracker()
1118 RegSubRegPair Def, in getNewSource() argument
1121 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1229 RegSubRegPair Def, RewriteMapTy &RewriteMap) { in rewriteSource() argument
1230 assert(!Register::isPhysicalRegister(Def.Reg) && in rewriteSource()
1234 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource()
1237 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1245 if (Def.SubReg) { in rewriteSource()
1246 NewCopy->getOperand(0).setSubReg(Def.SubReg); in rewriteSource()
1253 MRI->replaceRegWith(Def.Reg, NewVReg); in rewriteSource()
1284 RegSubRegPair Def; in optimizeUncoalescableCopy() local
1286 while (CpyRewriter.getNextRewritableSource(Src, Def)) { in optimizeUncoalescableCopy()
1289 if (Register::isPhysicalRegister(Def.Reg)) in optimizeUncoalescableCopy()
1294 if (!findNextSource(Def, RewriteMap)) in optimizeUncoalescableCopy()
1297 RewritePairs.push_back(Def); in optimizeUncoalescableCopy()
1301 for (const RegSubRegPair &Def : RewritePairs) { in optimizeUncoalescableCopy() local
1303 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap); in optimizeUncoalescableCopy()
1665 const auto &Def = NAPhysToVirtMIs.find(Reg); in runOnMachineFunction() local
1666 if (Def != NAPhysToVirtMIs.end()) { in runOnMachineFunction()
1671 NAPhysToVirtMIs.erase(Def); in runOnMachineFunction()
1677 Register Def = RegMI.first; in runOnMachineFunction() local
1678 if (MachineOperand::clobbersPhysReg(RegMask, Def)) { in runOnMachineFunction()
1681 NAPhysToVirtMIs.erase(Def); in runOnMachineFunction()
1809 assert(Def->isCopy() && "Invalid definition"); in getNextSourceFromCopy()
1814 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 && in getNextSourceFromCopy()
1816 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed"); in getNextSourceFromCopy()
1818 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1823 const MachineOperand &Src = Def->getOperand(1); in getNextSourceFromCopy()
1830 assert(Def->isBitcast() && "Invalid definition"); in getNextSourceFromBitcast()
1833 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects()) in getNextSourceFromBitcast()
1837 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
1839 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1845 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast()
1848 const MachineOperand &MO = Def->getOperand(OpIdx); in getNextSourceFromBitcast()
1863 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1873 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
1880 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
1883 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1906 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1924 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()
1927 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1940 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
1956 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
1977 assert((Def->isExtractSubreg() || in getNextSourceFromExtractSubreg()
1978 Def->isExtractSubregLike()) && "Invalid definition"); in getNextSourceFromExtractSubreg()
1993 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg)) in getNextSourceFromExtractSubreg()
2006 assert(Def->isSubregToReg() && "Invalid definition"); in getNextSourceFromSubregToReg()
2014 if (DefSubReg != Def->getOperand(3).getImm()) in getNextSourceFromSubregToReg()
2018 if (Def->getOperand(2).getSubReg()) in getNextSourceFromSubregToReg()
2021 return ValueTrackerResult(Def->getOperand(2).getReg(), in getNextSourceFromSubregToReg()
2022 Def->getOperand(3).getImm()); in getNextSourceFromSubregToReg()
2027 assert(Def->isPHI() && "Invalid definition"); in getNextSourceFromPHI()
2032 if (Def->getOperand(0).getSubReg() != DefSubReg) in getNextSourceFromPHI()
2036 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { in getNextSourceFromPHI()
2037 const MachineOperand &MO = Def->getOperand(i); in getNextSourceFromPHI()
2050 assert(Def && "This method needs a valid definition"); in getNextSourceImpl()
2052 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2053 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2054 Def->getDesc().isVariadic())) || in getNextSourceImpl()
2055 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
2057 if (Def->isCopy()) in getNextSourceImpl()
2059 if (Def->isBitcast()) in getNextSourceImpl()
2065 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
2067 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
2069 if (Def->isExtractSubreg() || Def->isExtractSubregLike()) in getNextSourceImpl()
2071 if (Def->isSubregToReg()) in getNextSourceImpl()
2073 if (Def->isPHI()) in getNextSourceImpl()
2081 if (!Def) in getNextSource()
2094 Res.setInst(Def); in getNextSource()
2101 Def = DI->getParent(); in getNextSource()
2105 Def = nullptr; in getNextSource()
2113 Def = nullptr; in getNextSource()