92       bool LiveOut = false;            ///< Register is possibly live out.  member
260                MCPhysReg AssignedReg, bool Kill, bool LiveOut);
389                          MCPhysReg AssignedReg, bool Kill, bool LiveOut) {  in spill()  argument
411     if (LiveOut) {  in spill()
604                        findLiveVirtReg(VirtReg)->LiveOut;  in calcSpillCost()
860         LRI->LiveOut = true;  in defineVirtReg()
879   if (LRI->Reloaded || LRI->LiveOut) {  in defineVirtReg()
883       LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut << " RL: "  in defineVirtReg()
886       spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);  in defineVirtReg()
889     LRI->LiveOut = false;  in defineVirtReg()
908         LRI->LiveOut = true;  in useVirtReg()
995       if (I->LiveOut || I->Reloaded) {  in dumpState()
997         if (I->LiveOut) dbgs() << 'O';  in dumpState()