Lines Matching refs:PhysReg
91 MCPhysReg PhysReg = 0; ///< Currently held here. member
148 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
149 bool isPhysRegFree(MCPhysReg PhysReg) const;
152 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
153 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
158 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr() argument
159 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in isRegUsedInInstr()
170 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr() argument
171 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markPhysRegUsedInInstr()
176 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr() argument
177 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in unmarkRegUsedInInstr()
221 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
222 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
223 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
224 void freePhysReg(MCPhysReg PhysReg);
226 unsigned calcSpillCost(MCPhysReg PhysReg) const;
236 void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
253 void setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
262 MCPhysReg PhysReg);
277 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { in setPhysRegState() argument
278 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) in setPhysRegState()
282 bool RegAllocFast::isPhysRegFree(MCPhysReg PhysReg) const { in isPhysRegFree()
283 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in isPhysRegFree()
434 MCPhysReg PhysReg) { in reload() argument
436 << printReg(PhysReg, TRI) << '\n'); in reload()
439 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI); in reload()
480 MCPhysReg Reg = P.PhysReg; in reloadAtBegin()
494 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin() local
495 if (PhysReg == 0) in reloadAtBegin()
498 MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI); in reloadAtBegin()
505 if (PrologLiveIns.count(PhysReg)) { in reloadAtBegin()
509 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
511 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
536 bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) { in displacePhysReg() argument
539 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in displacePhysReg()
547 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
549 setPhysRegState(LRI->PhysReg, regFree); in displacePhysReg()
550 LRI->PhysReg = 0; in displacePhysReg()
566 void RegAllocFast::freePhysReg(MCPhysReg PhysReg) { in freePhysReg() argument
567 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
569 MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI); in freePhysReg()
576 setPhysRegState(PhysReg, regFree); in freePhysReg()
582 setPhysRegState(LRI->PhysReg, regFree); in freePhysReg()
583 LRI->PhysReg = 0; in freePhysReg()
593 unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { in calcSpillCost()
594 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in calcSpillCost()
600 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
648 MCPhysReg PhysReg) { in assignVirtToPhysReg() argument
651 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
652 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
653 assert(PhysReg != 0 && "Trying to assign no register"); in assignVirtToPhysReg()
654 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
655 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
657 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
704 assert(LR.PhysReg == 0); in allocVirtReg()
750 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg() local
751 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' '); in allocVirtReg()
752 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) { in allocVirtReg()
757 unsigned Cost = calcSpillCost(PhysReg); in allocVirtReg()
761 assignVirtToPhysReg(MI, LR, PhysReg); in allocVirtReg()
765 if (PhysReg == Hint0 || PhysReg == Hint1) in allocVirtReg()
769 BestReg = PhysReg; in allocVirtReg()
783 LR.PhysReg = 0; in allocVirtReg()
797 MCPhysReg PhysReg; in allocVirtRegUndef() local
798 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in allocVirtRegUndef()
799 PhysReg = LRI->PhysReg; in allocVirtRegUndef()
804 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
809 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
812 MO.setReg(PhysReg); in allocVirtRegUndef()
822 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg()
827 LRI->PhysReg = 0; in defineLiveThroughVirtReg()
831 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to " in defineLiveThroughVirtReg()
835 .addReg(LRI->PhysReg, llvm::RegState::Kill); in defineLiveThroughVirtReg()
867 if (LRI->PhysReg == 0) in defineVirtReg()
870 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) && in defineVirtReg()
874 << printReg(LRI->PhysReg, TRI) << '\n'); in defineVirtReg()
877 MCPhysReg PhysReg = LRI->PhysReg; in defineVirtReg() local
878 assert(PhysReg != 0 && "Register not assigned"); in defineVirtReg()
886 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
892 markRegUsedInInstr(PhysReg); in defineVirtReg()
893 setPhysReg(MI, MO, PhysReg); in defineVirtReg()
919 if (LRI->PhysReg == 0) { in useVirtReg()
937 markRegUsedInInstr(LRI->PhysReg); in useVirtReg()
938 setPhysReg(MI, MO, LRI->PhysReg); in useVirtReg()
945 MCPhysReg PhysReg) { in setPhysReg() argument
947 MO.setReg(PhysReg); in setPhysReg()
953 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
964 MI.addRegisterKilled(PhysReg, TRI, true); in setPhysReg()
972 MI.addRegisterDead(PhysReg, TRI, true); in setPhysReg()
974 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
1001 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present"); in dumpState()
1011 MCPhysReg PhysReg = LR.PhysReg; in dumpState() local
1012 if (PhysReg != 0) { in dumpState()
1013 assert(Register::isPhysicalRegister(PhysReg) && in dumpState()
1015 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) { in dumpState()
1246 MCPhysReg PhysReg = LRI->PhysReg; in allocateInstruction() local
1247 if (PhysReg != 0 && MachineOperand::clobbersPhysReg(Mask, PhysReg)) in allocateInstruction()
1248 displacePhysReg(MI, PhysReg); in allocateInstruction()
1374 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in handleDebugValue()
1375 setPhysReg(MI, MO, LRI->PhysReg); in handleDebugValue()
1394 setPhysRegState(LI.PhysReg, regPreAssigned); in allocateBasicBlock()