Lines Matching refs:VirtReg
90 Register VirtReg; ///< Virtual register number. member
96 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
99 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
228 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
229 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
232 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
233 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
240 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
243 Register VirtReg);
244 void defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
246 void useVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg);
255 Register traceCopies(Register VirtReg) const;
258 int getStackSpaceFor(Register VirtReg);
259 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
261 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
264 bool mayLiveOut(Register VirtReg);
265 bool mayLiveIn(Register VirtReg);
292 int RegAllocFast::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor() argument
294 int SS = StackSlotForVirtReg[VirtReg]; in getStackSpaceFor()
300 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
306 StackSlotForVirtReg[VirtReg] = FrameIdx; in getStackSpaceFor()
325 bool RegAllocFast::mayLiveOut(Register VirtReg) { in mayLiveOut() argument
326 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) { in mayLiveOut()
336 SelfLoopDef = MRI->getUniqueVRegDef(VirtReg); in mayLiveOut()
338 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
347 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) { in mayLiveOut()
349 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
359 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
369 bool RegAllocFast::mayLiveIn(Register VirtReg) { in mayLiveIn() argument
370 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) in mayLiveIn()
376 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveIn()
378 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveIn()
388 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill() argument
390 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) in spill()
392 int FI = getStackSpaceFor(VirtReg); in spill()
395 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
404 SmallVectorImpl<MachineInstr *> &LRIDbgValues = LiveDbgValueMap[VirtReg]; in spill()
433 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, in reload() argument
435 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload()
437 int FI = getStackSpaceFor(VirtReg); in reload()
438 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
509 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
511 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
541 switch (unsigned VirtReg = RegUnitStates[Unit]) { in displacePhysReg() local
543 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in displacePhysReg()
547 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
570 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { in freePhysReg() local
579 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in freePhysReg()
581 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n'); in freePhysReg()
595 switch (unsigned VirtReg = RegUnitStates[*UI]) { in calcSpillCost() local
603 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 || in calcSpillCost()
604 findLiveVirtReg(VirtReg)->LiveOut; in calcSpillCost()
613 Register VirtReg, MCPhysReg Reg) { in assignDanglingDebugValues() argument
614 auto UDBGValIter = DanglingDbgValues.find(VirtReg); in assignDanglingDebugValues()
649 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg() local
650 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg()
655 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
657 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
683 Register RegAllocFast::traceCopies(Register VirtReg) const { in traceCopies()
686 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) { in traceCopies()
703 const Register VirtReg = LR.VirtReg; in allocVirtReg() local
706 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
707 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg) in allocVirtReg()
730 Register Hint1 = traceCopies(VirtReg); in allocVirtReg()
793 Register VirtReg = MO.getReg(); in allocVirtRegUndef() local
794 assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg"); in allocVirtRegUndef()
796 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg); in allocVirtRegUndef()
801 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
819 Register VirtReg) { in defineLiveThroughVirtReg() argument
820 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in defineLiveThroughVirtReg()
842 return defineVirtReg(MI, OpNum, VirtReg, true); in defineLiveThroughVirtReg()
851 Register VirtReg, bool LookAtPhysRegUses) { in defineVirtReg() argument
852 assert(VirtReg.isVirtual() && "Not a virtual register"); in defineVirtReg()
856 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); in defineVirtReg()
859 if (mayLiveOut(VirtReg)) { in defineVirtReg()
872 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI) in defineVirtReg()
886 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
898 Register VirtReg) { in useVirtReg() argument
899 assert(VirtReg.isVirtual() && "Not a virtual register"); in useVirtReg()
903 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); in useVirtReg()
907 if (mayLiveOut(VirtReg)) { in useVirtReg()
929 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in useVirtReg()
983 switch (unsigned VirtReg = RegUnitStates[Unit]) { in dumpState() local
992 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg); in dumpState()
993 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); in dumpState()
1009 Register VirtReg = LR.VirtReg; in dumpState() local
1010 assert(VirtReg.isVirtual() && "Bad map key"); in dumpState()
1016 assert(RegUnitStates[*UI] == VirtReg && "inverse map valid"); in dumpState()