Lines Matching refs:VirtReg
250 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
251 return ExtraRegInfo[VirtReg.reg()].Stage; in getStage()
254 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
256 ExtraRegInfo[VirtReg.reg()].Stage = Stage; in setStage()
466 Register canReassign(LiveInterval &VirtReg, Register PrevReg);
470 bool canEvictInterferenceInRange(LiveInterval &VirtReg, MCRegister PhysReg,
474 LiveInterval &VirtReg, SlotIndex Start,
478 bool mayRecolorAllInterferences(MCRegister PhysReg, LiveInterval &VirtReg,
491 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
497 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
502 MCRegister tryAssignCSRFirstTime(LiveInterval &VirtReg,
637 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) { in LRE_CanEraseVirtReg() argument
638 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_CanEraseVirtReg()
639 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
652 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
653 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
657 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
762 Register RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign() argument
769 if (!Matrix->checkInterference(VirtReg, *I)) { in tryAssign()
783 if (Register Hint = MRI->getSimpleHint(VirtReg.reg())) in tryAssign()
789 if (canEvictInterference(VirtReg, PhysHint, true, MaxCost, in tryAssign()
791 evictInterference(VirtReg, PhysHint, NewVRegs); in tryAssign()
796 SetOfBrokenHints.insert(&VirtReg); in tryAssign()
808 Register CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign()
816 Register RAGreedy::canReassign(LiveInterval &VirtReg, Register PrevReg) { in canReassign() argument
818 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in canReassign()
827 LiveIntervalUnion::Query subQ(VirtReg, Matrix->getLiveUnions()[*Units]); in canReassign()
836 LLVM_DEBUG(dbgs() << "can reassign: " << VirtReg << " from " in canReassign()
880 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, MCRegister PhysReg, in canEvictInterference() argument
884 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterference()
887 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg); in canEvictInterference()
896 unsigned Cascade = ExtraRegInfo[VirtReg.reg()].Cascade; in canEvictInterference()
902 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in canEvictInterference()
928 !VirtReg.isSpillable() && in canEvictInterference()
930 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterference()
953 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterference()
978 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg, in canEvictInterferenceInRange() argument
985 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in canEvictInterferenceInRange()
1030 LiveInterval &VirtReg, in getCheapestEvicteeWeight() argument
1035 BestEvictCost.MaxWeight = VirtReg.weight(); in getCheapestEvicteeWeight()
1041 if (!canEvictInterferenceInRange(VirtReg, PhysReg, Start, End, in getCheapestEvicteeWeight()
1055 void RAGreedy::evictInterference(LiveInterval &VirtReg, MCRegister PhysReg, in evictInterference() argument
1060 unsigned Cascade = ExtraRegInfo[VirtReg.reg()].Cascade; in evictInterference()
1062 Cascade = ExtraRegInfo[VirtReg.reg()].Cascade = NextCascade++; in evictInterference()
1070 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in evictInterference()
1086 LastEvicted.addEviction(PhysReg, VirtReg.reg(), Intf->reg()); in evictInterference()
1090 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
1112 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict() argument
1130 BestCost.MaxWeight = VirtReg.weight(); in tryEvict()
1133 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg()); in tryEvict()
1166 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost, in tryEvict()
1181 evictInterference(VirtReg, BestPhys, NewVRegs); in tryEvict()
1818 MCRegister RAGreedy::tryRegionSplit(LiveInterval &VirtReg, in tryRegionSplit() argument
1821 if (!TRI->shouldRegionSplitForVirtReg(*MF, VirtReg)) in tryRegionSplit()
1843 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands, in tryRegionSplit()
1859 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs); in tryRegionSplit()
1862 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost() argument
1953 << printReg(VirtReg.reg(), TRI) << " may "); in calculateRegionSplitCost()
1962 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, in doRegionSplit() argument
1967 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in doRegionSplit()
2009 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit() argument
2011 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed"); in tryBlockSplit()
2012 Register Reg = VirtReg.reg(); in tryBlockSplit()
2014 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryBlockSplit()
2075 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryInstructionSplit() argument
2077 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg()); in tryInstructionSplit()
2084 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryInstructionSplit()
2105 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
2123 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS); in tryInstructionSplit()
2218 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryLocalSplit() argument
2249 if (Matrix->checkRegMaskInterference(VirtReg)) { in tryLocalSplit()
2295 bool ProgressRequired = getStage(VirtReg) >= RS_Split2; in tryLocalSplit()
2314 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg)) in tryLocalSplit()
2410 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryLocalSplit()
2419 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS); in tryLocalSplit()
2449 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, in trySplit() argument
2453 if (getStage(VirtReg) >= RS_Spill) in trySplit()
2457 if (LIS->intervalIsInOneMBB(VirtReg)) { in trySplit()
2460 SA->analyze(&VirtReg); in trySplit()
2461 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs); in trySplit()
2464 return tryInstructionSplit(VirtReg, Order, NewVRegs); in trySplit()
2470 SA->analyze(&VirtReg); in trySplit()
2479 if (Register PhysReg = tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) in trySplit()
2486 if (getStage(VirtReg) < RS_Split2) { in trySplit()
2487 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); in trySplit()
2493 return tryBlockSplit(VirtReg, Order, NewVRegs); in trySplit()
2518 MCRegister PhysReg, LiveInterval &VirtReg, SmallLISet &RecoloringCandidates, in mayRecolorAllInterferences() argument
2520 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg()); in mayRecolorAllInterferences()
2523 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in mayRecolorAllInterferences()
2539 !(hasTiedDef(MRI, VirtReg.reg()) && in mayRecolorAllInterferences()
2591 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, in tryLastChanceRecoloring() argument
2596 if (!TRI->shouldUseLastChanceRecoloringForVirtReg(*MF, VirtReg)) in tryLastChanceRecoloring()
2599 LLVM_DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n'); in tryLastChanceRecoloring()
2601 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()
2620 assert(!FixedRegisters.count(VirtReg.reg())); in tryLastChanceRecoloring()
2621 FixedRegisters.insert(VirtReg.reg()); in tryLastChanceRecoloring()
2626 LLVM_DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " in tryLastChanceRecoloring()
2633 if (Matrix->checkInterference(VirtReg, PhysReg) > in tryLastChanceRecoloring()
2643 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates, in tryLastChanceRecoloring()
2670 Matrix->assign(VirtReg, PhysReg); in tryLastChanceRecoloring()
2683 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2687 LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " in tryLastChanceRecoloring()
2692 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2764 MCRegister RAGreedy::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
2769 MCRegister Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters); in selectOrSplit()
2795 RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order, in tryAssignCSRFirstTime() argument
2798 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()
2801 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
2810 if (getStage(VirtReg) < RS_Split) { in tryAssignCSRFirstTime()
2813 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
2816 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost, in tryAssignCSRFirstTime()
2823 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs); in tryAssignCSRFirstTime()
2903 void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { in tryHintRecoloring() argument
2910 Register Reg = VirtReg.reg(); in tryHintRecoloring()
3023 MCRegister RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, in selectOrSplitImpl() argument
3030 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplitImpl()
3032 tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) { in selectOrSplitImpl()
3034 LastEvicted.clearEvicteeInfo(VirtReg.reg()); in selectOrSplitImpl()
3040 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, in selectOrSplitImpl()
3050 LiveRangeStage Stage = getStage(VirtReg); in selectOrSplitImpl()
3052 << ExtraRegInfo[VirtReg.reg()].Cascade << '\n'); in selectOrSplitImpl()
3059 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit, in selectOrSplitImpl()
3061 Register Hint = MRI->getSimpleHint(VirtReg.reg()); in selectOrSplitImpl()
3068 SetOfBrokenHints.insert(&VirtReg); in selectOrSplitImpl()
3071 LastEvicted.clearEvicteeInfo(VirtReg.reg()); in selectOrSplitImpl()
3081 setStage(VirtReg, RS_Split); in selectOrSplitImpl()
3083 NewVRegs.push_back(VirtReg.reg()); in selectOrSplitImpl()
3090 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters); in selectOrSplitImpl()
3093 LastEvicted.clearEvicteeInfo(VirtReg.reg()); in selectOrSplitImpl()
3100 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplitImpl()
3101 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters, in selectOrSplitImpl()
3106 TRI->shouldUseDeferredSpillingForVirtReg(*MF, VirtReg)) && in selectOrSplitImpl()
3107 getStage(VirtReg) < RS_Memory) { in selectOrSplitImpl()
3112 setStage(VirtReg, RS_Memory); in selectOrSplitImpl()
3114 NewVRegs.push_back(VirtReg.reg()); in selectOrSplitImpl()
3118 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in selectOrSplitImpl()
3125 DebugVars->splitRegister(VirtReg.reg(), LRE.regs(), *LIS); in selectOrSplitImpl()