Lines Matching refs:SDep
256 SDep Dep; in addPhysRegDataDeps()
258 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
263 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
307 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
316 (Kind != SDep::Output || !MO.isDead() || in addPhysRegDeps()
318 SDep Dep(SU, Kind, /*Reg=*/*Alias); in addPhysRegDeps()
319 if (Kind != SDep::Anti) in addPhysRegDeps()
446 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
489 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
537 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
551 SDep Dep(SUa, SDep::MayAliasMem); in addChainDependency()
882 SDep Dep(SU, SDep::Artificial); in buildSchedGraph()
1204 bool ScheduleDAGInstrs::addEdge(SUnit *SuccSU, const SDep &PredDep) { in addEdge()
1283 for (const SDep &PredDep : SU->Preds) { in visitPostorderNode()
1284 if (PredDep.getKind() != SDep::Data) in visitPostorderNode()
1312 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) { in visitPostorderEdge()
1319 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) { in visitCrossEdge()
1362 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ, in joinPredSubtree()
1364 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges"); in joinPredSubtree()
1375 for (const SDep &SuccDep : PredSU->Succs) { in joinPredSubtree()
1376 if (SuccDep.getKind() == SDep::Data) { in joinPredSubtree()
1424 const SDep *backtrack() { in backtrack()
1441 for (const SDep &SuccDep : SU->Succs) { in hasDataSucc()
1442 if (SuccDep.getKind() == SDep::Data && in hasDataSucc()
1466 const SDep &PredDep = *DFS.getPred(); in compute()
1469 if (PredDep.getKind() != SDep::Data in compute()
1483 const SDep *PredDep = DFS.backtrack(); in compute()