Lines Matching refs:ZERO_EXTEND
1244 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1680 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
1792 case ISD::ZERO_EXTEND: in combine()
2198 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) in foldAddSubBoolOfMaskedVal()
2334 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && in visitADDLike()
2337 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not); in visitADDLike()
2574 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { in getAsCarry()
2678 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADDLikeCommutative()
3078 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND) in combineCarryDiamond()
3411 if (N1.getOpcode() == ISD::ZERO_EXTEND && in visitSUB()
4427 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
4428 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
4546 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); in visitUMUL_LOHI()
4547 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); in visitUMUL_LOHI()
4654 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND || in hoistLogicOpWithSameOpcodeHands()
5032 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And); in visitANDLike()
5208 case ISD::ZERO_EXTEND: in SearchForAndLoads()
5534 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), in visitAND()
5716 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && in visitAND()
5721 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0)); in visitAND()
5791 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0.getOperand(0)); in visitAND()
6870 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
6874 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || in MatchRotate()
7004 case ISD::ZERO_EXTEND: { in calculateByteProvider()
7012 return Op.getOpcode() == ISD::ZERO_EXTEND in calculateByteProvider()
7076 case ISD::ZERO_EXTEND: in stripTruncAndExt()
7639 if (isOneConstant(N1) && N0Opcode == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitXOR()
7646 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, V); in visitXOR()
8108 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in visitSHL()
8152 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && in visitSHL()
8171 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL); in visitSHL()
8299 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; in combineShiftToMULH()
9111 NotCond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, NotCond); in foldSelectOfConstants()
9124 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond); in foldSelectOfConstants()
9144 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond); in foldSelectOfConstants()
9157 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond); in foldSelectOfConstants()
9456 if (Index.getOpcode() == ISD::ZERO_EXTEND) { in refineIndexType()
9633 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in foldVSelectOfConstants()
9736 auto ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in visitVSELECT()
9979 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || in tryToFoldExtendOfConstant()
9997 (Opcode != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0.getValueType(), VT))) { in tryToFoldExtendOfConstant()
10033 Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG; in tryToFoldExtendOfConstant()
10076 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
10147 N->getOpcode() == ISD::ZERO_EXTEND) && in CombineExtLoad()
10242 assert(N->getOpcode() == ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
10283 ISD::ZERO_EXTEND, SetCCs, TLI)) in CombineZExtLogicopShiftLoad()
10300 ExtendSetCCUses(SetCCs, N1.getOperand(0), ExtLoad, ISD::ZERO_EXTEND); in CombineZExtLogicopShiftLoad()
10322 assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || in matchVSelectOpSizesWithSetCC()
10465 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); in foldExtendedSignBitTest()
10701 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && in visitSIGN_EXTEND()
10703 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0); in visitSIGN_EXTEND()
10712 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
10721 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitSIGN_EXTEND()
10730 (!LegalOperations || (TLI.isOperationLegal(ISD::ZERO_EXTEND, VT) && in visitSIGN_EXTEND()
10736 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitSIGN_EXTEND()
10780 assert((Extend->getOpcode() == ISD::ZERO_EXTEND || in widenCtPop()
10808 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) in visitZERO_EXTEND()
10809 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, in visitZERO_EXTEND()
10850 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) { in visitZERO_EXTEND()
10891 ISD::ZEXTLOAD, ISD::ZERO_EXTEND)) in visitZERO_EXTEND()
10896 ISD::ZERO_EXTEND)) in visitZERO_EXTEND()
10930 ISD::ZERO_EXTEND, SetCCs, TLI); in visitZERO_EXTEND()
10940 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::ZERO_EXTEND); in visitZERO_EXTEND()
11016 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC); in visitZERO_EXTEND()
11022 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && in visitZERO_EXTEND()
11039 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); in visitZERO_EXTEND()
11042 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), in visitZERO_EXTEND()
11066 N0.getOpcode() == ISD::ZERO_EXTEND || in visitANY_EXTEND()
11110 ISD::ZEXTLOAD, ISD::ZERO_EXTEND)) in visitANY_EXTEND()
11561 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in visitSIGN_EXTEND_INREG()
11734 if (N0.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
11985 N00.getOpcode() == ISD::ZERO_EXTEND || in visitTRUNCATE()
14145 if (N0.getOpcode() == ISD::ZERO_EXTEND && in visitSINT_TO_FP()
14231 : ISD::ZERO_EXTEND; in FoldIntToFPToInt()
15186 Val = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(LD), LDType, Val); in extendLoadedValueToExtension()
15634 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType)) in isLegal()
15695 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst); in loadSlice()
17791 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || in splitMergedValStore()
17794 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || in splitMergedValStore()
17816 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Lo.getOperand(0)); in splitMergedValStore()
17817 Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Hi.getOperand(0)); in splitMergedValStore()
18524 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; in reduceBuildVecExtToExtBuildVec()
18580 Cast.getOpcode() == ISD::ZERO_EXTEND || in reduceBuildVecExtToExtBuildVec()
18837 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || in reduceBuildVecToShuffleWithZero()
19116 FoundZeroExtend |= (Opc == ISD::ZERO_EXTEND); in convertBuildVecZextToZext()
19117 if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) && in convertBuildVecZextToZext()
19149 return DAG.getNode(FoundZeroExtend ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, DL, in convertBuildVecZextToZext()
21922 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC); in SimplifySelectCC()
21925 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC); in SimplifySelectCC()