1093                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
1103     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
1105   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1167                                        unsigned DefIdx) const {  in hasLowDefLatency()
1173   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1262                                        unsigned DefIdx,  in getOperandLatency()  argument
1267   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1287     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1293     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1297   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1314     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1320     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1324   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1339     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1345     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1349   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()