Lines Matching refs:ResultReg
368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
370 ResultReg) in fastMaterializeAlloca()
374 return ResultReg; in fastMaterializeAlloca()
391 unsigned ResultReg = createResultReg(RC); in materializeInt() local
393 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
394 return ResultReg; in materializeInt()
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
429 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
432 return ResultReg; in materializeFP()
445 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
446 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in materializeFP()
449 return ResultReg; in materializeFP()
469 unsigned ResultReg; in materializeGV() local
479 ResultReg = createResultReg(&AArch64::GPR32RegClass); in materializeGV()
482 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
486 ResultReg) in materializeGV()
491 return ResultReg; in materializeGV()
500 .addReg(ResultReg, RegState::Kill) in materializeGV()
509 ResultReg = createResultReg(&AArch64::GPR64spRegClass); in materializeGV()
511 ResultReg) in materializeGV()
517 return ResultReg; in materializeGV()
1054 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in simplifyAddress() local
1056 ResultReg) in simplifyAddress()
1061 Addr.setReg(ResultReg); in simplifyAddress()
1065 unsigned ResultReg = 0; in simplifyAddress() local
1069 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1074 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1080 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1084 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1088 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1091 if (!ResultReg) in simplifyAddress()
1094 Addr.setReg(ResultReg); in simplifyAddress()
1103 unsigned ResultReg; in simplifyAddress() local
1106 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset); in simplifyAddress()
1108 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset); in simplifyAddress()
1110 if (!ResultReg) in simplifyAddress()
1112 Addr.setReg(ResultReg); in simplifyAddress()
1210 unsigned ResultReg = 0; in emitAddSub() local
1214 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1217 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1221 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1224 if (ResultReg) in emitAddSub()
1225 return ResultReg; in emitAddSub()
1265 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1268 if (ResultReg) in emitAddSub()
1269 return ResultReg; in emitAddSub()
1290 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1293 if (ResultReg) in emitAddSub()
1294 return ResultReg; in emitAddSub()
1335 unsigned ResultReg; in emitAddSub_rr() local
1337 ResultReg = createResultReg(RC); in emitAddSub_rr()
1339 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rr()
1344 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rr()
1347 return ResultReg; in emitAddSub_rr()
1380 unsigned ResultReg; in emitAddSub_ri() local
1382 ResultReg = createResultReg(RC); in emitAddSub_ri()
1384 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_ri()
1388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_ri()
1392 return ResultReg; in emitAddSub_ri()
1422 unsigned ResultReg; in emitAddSub_rs() local
1424 ResultReg = createResultReg(RC); in emitAddSub_rs()
1426 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rs()
1431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rs()
1435 return ResultReg; in emitAddSub_rs()
1467 unsigned ResultReg; in emitAddSub_rx() local
1469 ResultReg = createResultReg(RC); in emitAddSub_rx()
1471 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rx()
1476 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rx()
1480 return ResultReg; in emitAddSub_rx()
1565 unsigned ResultReg; in emitAdd_ri_() local
1567 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm); in emitAdd_ri_()
1569 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm); in emitAdd_ri_()
1571 if (ResultReg) in emitAdd_ri_()
1572 return ResultReg; in emitAdd_ri_()
1578 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true); in emitAdd_ri_()
1579 return ResultReg; in emitAdd_ri_()
1627 unsigned ResultReg = 0; in emitLogicalOp() local
1630 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1632 if (ResultReg) in emitLogicalOp()
1633 return ResultReg; in emitLogicalOp()
1652 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1654 if (ResultReg) in emitLogicalOp()
1655 return ResultReg; in emitLogicalOp()
1668 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1670 if (ResultReg) in emitLogicalOp()
1671 return ResultReg; in emitLogicalOp()
1681 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in emitLogicalOp()
1684 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp()
1686 return ResultReg; in emitLogicalOp()
1725 unsigned ResultReg = in emitLogicalOp_ri() local
1730 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_ri()
1732 return ResultReg; in emitLogicalOp_ri()
1768 unsigned ResultReg = in emitLogicalOp_rs() local
1773 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_rs()
1775 return ResultReg; in emitLogicalOp_rs()
1894 unsigned ResultReg = createResultReg(RC); in emitLoad() local
1896 TII.get(Opc), ResultReg); in emitLoad()
1901 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1); in emitLoad()
1903 ResultReg = ANDReg; in emitLoad()
1913 .addReg(ResultReg, getKillRegState(true)) in emitLoad()
1915 ResultReg = Reg64; in emitLoad()
1917 return ResultReg; in emitLoad()
1928 unsigned ResultReg; in selectAddSub() local
1933 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1936 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1939 if (!ResultReg) in selectAddSub()
1942 updateValueMap(I, ResultReg); in selectAddSub()
1954 unsigned ResultReg; in selectLogicalOp() local
1959 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1962 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1965 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1968 if (!ResultReg) in selectLogicalOp()
1971 updateValueMap(I, ResultReg); in selectLogicalOp()
2023 unsigned ResultReg = in selectLoad() local
2025 if (!ResultReg) in selectLoad()
2051 ResultReg = std::prev(I)->getOperand(0).getReg(); in selectLoad()
2054 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, in selectLoad()
2058 updateValueMap(I, ResultReg); in selectLoad()
2079 updateValueMap(IntExtVal, ResultReg); in selectLoad()
2083 updateValueMap(I, ResultReg); in selectLoad()
2575 unsigned ResultReg = 0; in selectCmp() local
2580 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2582 TII.get(TargetOpcode::COPY), ResultReg) in selectCmp()
2586 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1); in selectCmp()
2590 if (ResultReg) { in selectCmp()
2591 updateValueMap(I, ResultReg); in selectCmp()
2599 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2627 ResultReg) in selectCmp()
2632 updateValueMap(I, ResultReg); in selectCmp()
2641 ResultReg) in selectCmp()
2646 updateValueMap(I, ResultReg); in selectCmp()
2701 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect() local
2703 updateValueMap(SI, ResultReg); in optimizeSelect()
2831 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() local
2833 updateValueMap(I, ResultReg); in selectSelect()
2846 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); in selectFPExt() local
2848 ResultReg).addReg(Op); in selectFPExt()
2849 updateValueMap(I, ResultReg); in selectFPExt()
2862 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); in selectFPTrunc() local
2864 ResultReg).addReg(Op); in selectFPTrunc()
2865 updateValueMap(I, ResultReg); in selectFPTrunc()
2895 unsigned ResultReg = createResultReg( in selectFPToInt() local
2897 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in selectFPToInt()
2899 updateValueMap(I, ResultReg); in selectFPToInt()
2943 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP() local
2945 updateValueMap(I, ResultReg); in selectIntToFP()
3051 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
3053 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerArguments()
3055 updateValueMap(&Arg, ResultReg); in fastLowerArguments()
3176 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall() local
3178 TII.get(TargetOpcode::COPY), ResultReg) in finishCall()
3182 CLI.ResultReg = ResultReg; in finishCall()
3366 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy() local
3367 if (!ResultReg) in tryEmitSmallMemCpy()
3370 if (!emitStore(VT, ResultReg, Dest)) in tryEmitSmallMemCpy()
3510 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastLowerIntrinsicCall() local
3512 TII.get(AArch64::ADDXri), ResultReg) in fastLowerIntrinsicCall()
3517 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3621 updateValueMap(II, CLI.ResultReg); in fastLowerIntrinsicCall()
3644 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall() local
3645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3647 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3671 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); in fastLowerIntrinsicCall() local
3672 if (!ResultReg) in fastLowerIntrinsicCall()
3675 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3972 unsigned ResultReg; in selectTrunc() local
3993 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask); in selectTrunc()
3994 assert(ResultReg && "Unexpected AND instruction emission failure."); in selectTrunc()
3996 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
3998 TII.get(TargetOpcode::COPY), ResultReg) in selectTrunc()
4002 updateValueMap(I, ResultReg); in selectTrunc()
4015 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); in emiti1Ext() local
4016 assert(ResultReg && "Unexpected AND instruction emission failure."); in emiti1Ext()
4024 .addReg(ResultReg) in emiti1Ext()
4026 ResultReg = Reg64; in emiti1Ext()
4028 return ResultReg; in emiti1Ext()
4098 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr() local
4101 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSL_rr()
4102 return ResultReg; in emitLSL_rr()
4126 unsigned ResultReg = createResultReg(RC); in emitLSL_ri() local
4128 TII.get(TargetOpcode::COPY), ResultReg) in emitLSL_ri()
4130 return ResultReg; in emitLSL_ri()
4205 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr() local
4208 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSR_rr()
4209 return ResultReg; in emitLSR_rr()
4233 unsigned ResultReg = createResultReg(RC); in emitLSR_ri() local
4235 TII.get(TargetOpcode::COPY), ResultReg) in emitLSR_ri()
4237 return ResultReg; in emitLSR_ri()
4326 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitASR_rr() local
4329 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitASR_rr()
4330 return ResultReg; in emitASR_rr()
4354 unsigned ResultReg = createResultReg(RC); in emitASR_ri() local
4356 TII.get(TargetOpcode::COPY), ResultReg) in emitASR_ri()
4358 return ResultReg; in emitASR_ri()
4603 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); in selectIntExt() local
4605 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
4609 SrcReg = ResultReg; in selectIntExt()
4624 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt() local
4625 if (!ResultReg) in selectIntExt()
4628 updateValueMap(I, ResultReg); in selectIntExt()
4671 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true, in selectRem() local
4674 updateValueMap(I, ResultReg); in selectRem()
4723 unsigned ResultReg = in selectMul() local
4726 if (ResultReg) { in selectMul()
4727 updateValueMap(I, ResultReg); in selectMul()
4742 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() local
4744 if (!ResultReg) in selectMul()
4747 updateValueMap(I, ResultReg); in selectMul()
4760 unsigned ResultReg = 0; in selectShift() local
4793 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4796 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4799 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4802 if (!ResultReg) in selectShift()
4805 updateValueMap(I, ResultReg); in selectShift()
4819 unsigned ResultReg = 0; in selectShift() local
4823 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4826 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4829 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4833 if (!ResultReg) in selectShift()
4836 updateValueMap(I, ResultReg); in selectShift()
4872 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); in selectBitCast() local
4874 if (!ResultReg) in selectBitCast()
4877 updateValueMap(I, ResultReg); in selectBitCast()
4915 updateValueMap(I, CLI.ResultReg); in selectFRem()
4939 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() local
4940 if (!ResultReg) in selectSDiv()
4942 updateValueMap(I, ResultReg); in selectSDiv()
4973 unsigned ResultReg; in selectSDiv() local
4975 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true, in selectSDiv()
4978 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
4980 if (!ResultReg) in selectSDiv()
4983 updateValueMap(I, ResultReg); in selectSDiv()